alu.fit.eqn

ALU可以实现16种操作（包括加减乘除移位运算等）

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L212 is Mux~10118 at LC_X8_Y12_N6
--operation mode is normal

A1L212 = OP[2] & !OP[1];


--A1L312 is Mux~10119 at LC_X9_Y15_N8
--operation mode is normal

B2_Q[0]_qfbk = B2_Q[0];
A1L312 = A1L212 & (OP[0] & H1_decoder_node[0][0] # !OP[0] & (!B2_Q[0]_qfbk));

--B2_Q[0] is reg:B_reg|Q[0] at LC_X9_Y15_N8
--operation mode is normal

B2_Q[0] = DFFEAS(A1L312, GLOBAL(clk), GLOBAL(reset), , B2L1, Dinput[0], , , VCC);


--A1L1 is add~1351 at LC_X10_Y11_N2
--operation mode is arithmetic

A1L1 = B1_Q[0] $ B2_Q[0] $ A1L281;

--A1L2 is add~1353 at LC_X10_Y11_N2
--operation mode is arithmetic

A1L2_cout_0 = B1_Q[0] & !B2_Q[0] & !A1L281 # !B1_Q[0] & (!A1L281 # !B2_Q[0]);
A1L2 = CARRY(A1L2_cout_0);

--A1L3 is add~1353COUT1_1729 at LC_X10_Y11_N2
--operation mode is arithmetic

A1L3_cout_1 = B1_Q[0] & !B2_Q[0] & !A1L381 # !B1_Q[0] & (!A1L381 # !B2_Q[0]);
A1L3 = CARRY(A1L3_cout_1);


--A1L4 is add~1356 at LC_X10_Y13_N2
--operation mode is arithmetic

A1L4 = B1_Q[0] $ B2_Q[0] $ !A1L581;

--A1L5 is add~1358 at LC_X10_Y13_N2
--operation mode is arithmetic

A1L5_cout_0 = B1_Q[0] & B2_Q[0] & !A1L581 # !B1_Q[0] & (B2_Q[0] # !A1L581);
A1L5 = CARRY(A1L5_cout_0);

--A1L6 is add~1358COUT1_1743 at LC_X10_Y13_N2
--operation mode is arithmetic

A1L6_cout_1 = B1_Q[0] & B2_Q[0] & !A1L681 # !B1_Q[0] & (B2_Q[0] # !A1L681);
A1L6 = CARRY(A1L6_cout_1);


--A1L412 is Mux~10120 at LC_X9_Y15_N3
--operation mode is normal

B2_Q[1]_qfbk = B2_Q[1];
A1L412 = OP[1] & (A1L4 # !OP[0]) # !OP[1] & OP[0] & B2_Q[1]_qfbk;

--B2_Q[1] is reg:B_reg|Q[1] at LC_X9_Y15_N3
--operation mode is normal

B2_Q[1] = DFFEAS(A1L412, GLOBAL(clk), GLOBAL(reset), , B2L1, Dinput[1], , , VCC);


--A1L512 is Mux~10121 at LC_X9_Y15_N0
--operation mode is normal

A1L512 = !OP[2] & A1L412 & (OP[0] # A1L1);


--A1L612 is Mux~10122 at LC_X9_Y15_N4
--operation mode is normal

B1_Q[0]_qfbk = B1_Q[0];
A1L612 = B2_Q[0] & (OP[0] $ B1_Q[0]_qfbk # !OP[1]) # !B2_Q[0] & B1_Q[0]_qfbk & (OP[1] $ !OP[0]);

--B1_Q[0] is reg:A_reg|Q[0] at LC_X9_Y15_N4
--operation mode is normal

B1_Q[0] = DFFEAS(A1L612, GLOBAL(clk), GLOBAL(reset), , B1L1, Dinput[0], , , VCC);


--F1L21 is adder16:l1|add4:u1|sum~0 at LC_X11_Y11_N5
--operation mode is normal

F1L21 = B2_Q[0] $ B1_Q[0];


--A1L7 is add~1361 at LC_X9_Y13_N2
--operation mode is arithmetic

A1L7 = !B1_Q[0];

--A1L8 is add~1363 at LC_X9_Y13_N2
--operation mode is arithmetic

A1L8_cout_0 = B1_Q[0];
A1L8 = CARRY(A1L8_cout_0);

--A1L9 is add~1363COUT1_1702 at LC_X9_Y13_N2
--operation mode is arithmetic

A1L9_cout_1 = B1_Q[0];
A1L9 = CARRY(A1L9_cout_1);


--A1L01 is add~1366 at LC_X8_Y14_N2
--operation mode is arithmetic

A1L01 = !B1_Q[0];

--A1L11 is add~1368 at LC_X8_Y14_N2
--operation mode is arithmetic

A1L11_cout_0 = B1_Q[0];
A1L11 = CARRY(A1L11_cout_0);

--A1L21 is add~1368COUT1_1715 at LC_X8_Y14_N2
--operation mode is arithmetic

A1L21_cout_1 = B1_Q[0];
A1L21 = CARRY(A1L21_cout_1);


--A1L712 is Mux~10123 at LC_X7_Y8_N2
--operation mode is normal

A1L712 = OP[0] & (A1L7) # !OP[0] & A1L01;


--A1L812 is Mux~10124 at LC_X9_Y15_N1
--operation mode is normal

A1L812 = OP[1] & (OP[2] & (A1L683) # !OP[2] & A1L612) # !OP[1] & (OP[2] & A1L612 # !OP[2] & (A1L683));


--A1L912 is Mux~10125 at LC_X9_Y15_N2
--operation mode is normal

A1L912 = OP[3] & (A1L512 # A1L312) # !OP[3] & A1L812;


--A1L31 is add~1371 at LC_X10_Y11_N3
--operation mode is arithmetic

A1L31 = B1_Q[1] $ B2_Q[1] $ !A1L2;

--A1L41 is add~1373 at LC_X10_Y11_N3
--operation mode is arithmetic

A1L41_cout_0 = B1_Q[1] & (B2_Q[1] # !A1L2) # !B1_Q[1] & B2_Q[1] & !A1L2;
A1L41 = CARRY(A1L41_cout_0);

--A1L51 is add~1373COUT1_1730 at LC_X10_Y11_N3
--operation mode is arithmetic

A1L51_cout_1 = B1_Q[1] & (B2_Q[1] # !A1L3) # !B1_Q[1] & B2_Q[1] & !A1L3;
A1L51 = CARRY(A1L51_cout_1);


--A1L022 is Mux~10126 at LC_X10_Y14_N0
--operation mode is normal

B1_Q[1]_qfbk = B1_Q[1];
A1L022 = OP[3] & (OP[0]) # !OP[3] & (B2_Q[1] & (B1_Q[1]_qfbk $ OP[0]) # !B2_Q[1] & B1_Q[1]_qfbk & OP[0]);

--B1_Q[1] is reg:A_reg|Q[1] at LC_X10_Y14_N0
--operation mode is normal

B1_Q[1] = DFFEAS(A1L022, GLOBAL(clk), GLOBAL(reset), , B1L1, Dinput[1], , , VCC);


--A1L61 is add~1376 at LC_X10_Y13_N3
--operation mode is arithmetic

A1L61 = B2_Q[1] $ B1_Q[1] $ A1L5;

--A1L71 is add~1378 at LC_X10_Y13_N3
--operation mode is arithmetic

A1L71_cout_0 = B2_Q[1] & B1_Q[1] & !A1L5 # !B2_Q[1] & (B1_Q[1] # !A1L5);
A1L71 = CARRY(A1L71_cout_0);

--A1L81 is add~1378COUT1_1744 at LC_X10_Y13_N3
--operation mode is arithmetic

A1L81_cout_1 = B2_Q[1] & B1_Q[1] & !A1L6 # !B2_Q[1] & (B1_Q[1] # !A1L6);
A1L81 = CARRY(A1L81_cout_1);


--A1L122 is Mux~10127 at LC_X10_Y15_N0
--operation mode is normal

A1L122 = A1L022 & (A1L61 # !OP[3]) # !A1L022 & A1L31 & (OP[3]);


--A1L222 is Mux~10128 at LC_X7_Y9_N9
--operation mode is normal

A1L222 = OP[1] & (OP[0] # !OP[2]);


--A1L91 is add~1381 at LC_X8_Y14_N3
--operation mode is arithmetic

A1L91 = B1_Q[1] $ !A1L11;

--A1L02 is add~1383 at LC_X8_Y14_N3
--operation mode is arithmetic

A1L02_cout_0 = !B1_Q[1] & !A1L11;
A1L02 = CARRY(A1L02_cout_0);

--A1L12 is add~1383COUT1_1716 at LC_X8_Y14_N3
--operation mode is arithmetic

A1L12_cout_1 = !B1_Q[1] & !A1L21;
A1L12 = CARRY(A1L12_cout_1);


--A1L322 is Mux~10129 at LC_X7_Y8_N4
--operation mode is normal

A1L322 = OP[1] & (OP[2]);


--F5_sum[1] is sub16:l2|adder16:l1|add4:u1|sum[1] at LC_X10_Y15_N2
--operation mode is normal

F5_sum[1] = B2_Q[1] $ B1_Q[1] $ (B1_Q[0] # !B2_Q[0]);


--F1_sum[1] is adder16:l1|add4:u1|sum[1] at LC_X10_Y15_N4
--operation mode is normal

F1_sum[1] = B2_Q[1] $ B1_Q[1] $ (B1_Q[0] & B2_Q[0]);


--A1L422 is Mux~10130 at LC_X10_Y15_N5
--operation mode is normal

A1L422 = OP[0] & (OP[3] # !F5_sum[1]) # !OP[0] & !OP[3] & (F1_sum[1]);


--A1L522 is Mux~10131 at LC_X10_Y15_N6
--operation mode is normal

B2_Q[2]_qfbk = B2_Q[2];
A1L522 = OP[3] & (A1L422 & (B2_Q[2]_qfbk) # !A1L422 & B2_Q[0]) # !OP[3] & (A1L422);

--B2_Q[2] is reg:B_reg|Q[2] at LC_X10_Y15_N6
--operation mode is normal

B2_Q[2] = DFFEAS(A1L522, GLOBAL(clk), GLOBAL(reset), , B2L1, Dinput[2], , , VCC);


--A1L622 is Mux~10132 at LC_X10_Y15_N1
--operation mode is normal

A1L622 = A1L222 & (A1L322) # !A1L222 & (A1L322 & A1L91 # !A1L322 & (A1L522));


--A1L22 is add~1386 at LC_X9_Y13_N3
--operation mode is arithmetic

A1L22 = B1_Q[1] $ (A1L8);

--A1L32 is add~1388 at LC_X9_Y13_N3
--operation mode is arithmetic

A1L32_cout_0 = !A1L8 # !B1_Q[1];
A1L32 = CARRY(A1L32_cout_0);

--A1L42 is add~1388COUT1_1703 at LC_X9_Y13_N3
--operation mode is arithmetic

A1L42_cout_1 = !A1L9 # !B1_Q[1];
A1L42 = CARRY(A1L42_cout_1);


--A1L722 is Mux~10133 at LC_X10_Y15_N9
--operation mode is normal

A1L722 = A1L222 & (A1L622 & A1L22 # !A1L622 & (A1L122)) # !A1L222 & (A1L622);


--A1L822 is Mux~10134 at LC_X9_Y14_N8
--operation mode is normal

A1L822 = A1L722 & (!OP[3] & OP[1] # !OP[2]);


--A1L922 is Mux~10135 at LC_X10_Y14_N4
--operation mode is normal

A1L922 = !OP[3] & (B2_Q[1] # !OP[0] & B1_Q[1]);


--M3L1 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~61 at LC_X12_Y12_N0
--operation mode is arithmetic

M3L1 = H1_decoder_node[0][1] $ H1_decoder_node[1][0];

--M3L2 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~63 at LC_X12_Y12_N0
--operation mode is arithmetic

M3L2_cout_0 = H1_decoder_node[0][1] & H1_decoder_node[1][0];
M3L2 = CARRY(M3L2_cout_0);

--M3L3 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~63COUT1_107 at LC_X12_Y12_N0
--operation mode is arithmetic

M3L3_cout_1 = H1_decoder_node[0][1] & H1_decoder_node[1][0];
M3L3 = CARRY(M3L3_cout_1);


--A1L032 is Mux~10136 at LC_X10_Y14_N5
--operation mode is normal

A1L032 = OP[3] & (OP[0] & (M3L1) # !OP[0] & !B2_Q[1]);


--A1L132 is Mux~10137 at LC_X10_Y14_N9
--operation mode is normal

A1L132 = A1L822 # A1L212 & (A1L922 # A1L032);


--A1L52 is add~1391 at LC_X10_Y11_N4
--operation mode is arithmetic

A1L52 = B1_Q[2] $ B2_Q[2] $ A1L41;

--A1L62 is add~1393 at LC_X10_Y11_N4
--operation mode is arithmetic

A1L62 = CARRY(B1_Q[2] & !B2_Q[2] & !A1L51 # !B1_Q[2] & (!A1L51 # !B2_Q[2]));


--A1L232 is Mux~10138 at LC_X10_Y14_N7
--operation mode is normal

B1_Q[2]_qfbk = B1_Q[2];
A1L232 = OP[3] & (OP[0]) # !OP[3] & (B2_Q[2] & (B1_Q[2]_qfbk $ OP[0]) # !B2_Q[2] & B1_Q[2]_qfbk & OP[0]);

--B1_Q[2] is reg:A_reg|Q[2] at LC_X10_Y14_N7
--operation mode is normal

B1_Q[2] = DFFEAS(A1L232, GLOBAL(clk), GLOBAL(reset), , B1L1, Dinput[2], , , VCC);


--A1L72 is add~1396 at LC_X10_Y13_N4
--operation mode is arithmetic

A1L72 = B1_Q[2] $ B2_Q[2] $ !A1L71;

--A1L82 is add~1398 at LC_X10_Y13_N4
--operation mode is arithmetic

A1L82 = CARRY(B1_Q[2] & B2_Q[2] & !A1L81 # !B1_Q[2] & (B2_Q[2] # !A1L81));


--A1L332 is Mux~10139 at LC_X11_Y14_N9
--operation mode is normal

A1L332 = A1L232 & (A1L72 # !OP[3]) # !A1L232 & A1L52 & OP[3];


--A1L92 is add~1401 at LC_X8_Y14_N4
--operation mode is arithmetic

A1L92 = B1_Q[2] $ (A1L02);

--A1L03 is add~1403 at LC_X8_Y14_N4
--operation mode is arithmetic

A1L03 = CARRY(B1_Q[2] # !A1L12);


--F5L21 is sub16:l2|adder16:l1|add4:u1|temp3~37 at LC_X12_Y14_N6
--operation mode is normal

F5L21 = !B2_Q[1] & B1_Q[1];


--F5L1 is sub16:l2|adder16:l1|add4:u1|c2~56 at LC_X12_Y14_N8
--operation mode is normal

F5L1 = B1_Q[0] & (B1_Q[1] # !B2_Q[1]) # !B1_Q[0] & !B2_Q[0] & (B1_Q[1] # !B2_Q[1]);


--F5_sum[2] is sub16:l2|adder16:l1|add4:u1|sum[2] at LC_X12_Y14_N7
--operation mode is normal

F5_sum[2] = B2_Q[2] $ B1_Q[2] $ (F5L1 # F5L21);


--F1L1 is adder16:l1|add4:u1|c2~7 at LC_X13_Y14_N1
--operation mode is normal

F1L1 = B2_Q[1] & (B1_Q[1] # B2_Q[0] & B1_Q[0]) # !B2_Q[1] & B2_Q[0] & B1_Q[0] & B1_Q[1];


--F1_sum[2] is adder16:l1|add4:u1|sum[2] at LC_X13_Y14_N2
--operation mode is normal

F1_sum[2] = B1_Q[2] $ B2_Q[2] $ F1L1;


--A1L432 is Mux~10140 at LC_X11_Y15_N1
--operation mode is normal

A1L432 = OP[0] & (OP[3] # !F5_sum[2]) # !OP[0] & (!OP[3] & F1_sum[2]);


--A1L532 is Mux~10141 at LC_X11_Y15_N0
--operation mode is normal

B2_Q[3]_qfbk = B2_Q[3];
A1L532 = OP[3] & (A1L432 & (B2_Q[3]_qfbk) # !A1L432 & B2_Q[1]) # !OP[3] & (A1L432);

--B2_Q[3] is reg:B_reg|Q[3] at LC_X11_Y15_N0
--operation mode is normal

B2_Q[3] = DFFEAS(A1L532, GLOBAL(clk), GLOBAL(reset), , B2L1, Dinput[3], , , VCC);


--A1L632 is Mux~10142 at LC_X8_Y14_N0
--operation mode is normal

A1L632 = A1L322 & (A1L92 # A1L222) # !A1L322 & A1L532 & (!A1L222);


--A1L13 is add~1406 at LC_X9_Y13_N4
--operation mode is arithmetic

A1L13 = B1_Q[2] $ !A1L32;

--A1L23 is add~1408 at LC_X9_Y13_N4
--operation mode is arithmetic

A1L23 = CARRY(B1_Q[2] & !A1L42);


--A1L732 is Mux~10143 at LC_X11_Y14_N6
--operation mode is normal

A1L732 = A1L632 & (A1L13 # !A1L222) # !A1L632 & (A1L332 & A1L222);


--A1L832 is Mux~10144 at LC_X9_Y14_N4
--operation mode is normal

A1L832 = A1L732 & (!OP[3] & OP[1] # !OP[2]);


--M51L1 is lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~70 at LC_X12_Y11_N0
--operation mode is arithmetic

M51L1 = M3L4 $ H1_decoder_node[2][0];