spmc75f2413a.inc

实现写字功能,可以单个字,也可以多个字.功能挺多的.

.DEFINE CW_WDPS_FCKdiv4096			0x0004
.DEFINE CW_WDPS_FCKdiv2048			0x0005
.DEFINE CW_WDPS_FCKdiv1024			0x0006
.DEFINE CW_WDPS_FCKdiv512			0x0007

.DEFINE CW_WDCHK_Setting			(0x0015 << 3)
.DEFINE CW_WDRS_SYS_Reset			(0x0000 << 14)
.DEFINE CW_WDRS_CPU_Reset			(0x0001 << 14)
.DEFINE CW_WDEN						(0x0001 << 15)
.DEFINE CW_WatchDog_Clear			0xA005

// Bit set //
.DEFINE CB_WDPS0						0
.DEFINE CB_WDPS1						1
.DEFINE CB_WDPS2						2
.DEFINE CB_WDCHK0						3
.DEFINE CB_WDCHK1						4
.DEFINE CB_WDCHK2						5
.DEFINE CB_WDCHK3						6
.DEFINE CB_WDCHK4						7
.DEFINE CB_WDRS							14
.DEFINE CB_WDEN							15

// P_Wakeup_Ctrl register // 
// word set //
.DEFINE CW_CMTWE_Enable				(0x0001<<4)
.DEFINE CW_PDC0WE_Enable			(0x0001<<5)
.DEFINE CW_PDC1WE_Enable			(0x0001<<6)
.DEFINE CW_TPM2WE_Enable			(0x0001<<7)
.DEFINE CW_EXT0WE_Enable			(0x0001<<11)
.DEFINE CW_EXT1WE_Enable			(0x0001<<12)
.DEFINE CW_SPIWE_Enable				(0x0001<<13)
.DEFINE CW_UARTWE_Enable			(0x0001<<14)
.DEFINE CW_KEYWE_Enable				(0x0001<<15)

// Bit set //
.DEFINE CB_CMTWE_Enable					4
.DEFINE CB_PDC0WE_Enable				5
.DEFINE CB_PDC1WE_Enable				6
.DEFINE CB_TPM2WE_Enable				7
.DEFINE CB_EXT0WE_Enable				11
.DEFINE CB_EXT1WE_Enable				12
.DEFINE CB_SPIWE_Enable					13
.DEFINE CB_UARTWE_Enable				14
.DEFINE CB_KEYWE_Enable					15

// P_Flash_RW register //
// word set //
.DEFINE	CW_BK15WDIS					0x4000			//BANK 15 Write Disable
.DEFINE	CW_BK14WDIS					0x4000			//BANK 14 Write Disable
.DEFINE	CW_BK13WDIS					0x2000			//BANK 13 Write Disable
.DEFINE	CW_BK12WDIS					0x1000			//BANK 12 Write Disable
.DEFINE	CW_BK11WDIS					0x0800			//BANK 11 Write Disable
.DEFINE	CW_BK10WDIS					0x0400			//BANK 10 Write Disable
.DEFINE	CW_BK9WDIS					0x0200			//BANK 9 Write Disable
.DEFINE	CW_BK8WDIS					0x0100			//BANK 8 Write Disable
.DEFINE	CW_BK7WDIS					0x0080			//BANK 7 Write Disable
.DEFINE	CW_BK6WDIS					0x0040			//BANK 6 Write Disable
.DEFINE	CW_BK5WDIS					0x0020			//BANK 5 Write Disable
.DEFINE	CW_BK4WDIS					0x0010			//BANK 4 Write Disable
.DEFINE	CW_BK3WDIS					0x0008			//BANK 3 Write Disable
.DEFINE	CW_BK2WDIS					0x0004			//BANK 2 Write Disable
.DEFINE	CW_BK1WDIS					0x0002			//BANK 1 Write Disable
.DEFINE	CW_BK0WDIS					0x0001			//BANK 0 Write Disable

// Bit set //
.DEFINE	CB_BK14WDIS						14			//BANK 14 Write Disable
.DEFINE	CB_BK13WDIS						13			//BANK 13 Write Disable
.DEFINE	CB_BK12WDIS						12			//BANK 12 Write Disable
.DEFINE	CB_BK11WDIS						11			//BANK 11 Write Disable
.DEFINE	CB_BK10WDIS						10			//BANK 10 Write Disable
.DEFINE	CB_BK9WDIS						9			//BANK 9 Write Disable
.DEFINE	CB_BK8WDIS						8			//BANK 8 Write Disable
.DEFINE	CB_BK7WDIS						7			//BANK 7 Write Disable
.DEFINE	CB_BK6WDIS						6			//BANK 6 Write Disable
.DEFINE	CB_BK5WDIS						5			//BANK 5 Write Disable
.DEFINE	CB_BK4WDIS						4			//BANK 4 Write Disable
.DEFINE	CB_BK3WDIS						3			//BANK 3 Write Disable
.DEFINE	CB_BK2WDIS						2			//BANK 2 Write Disable
.DEFINE	CB_BK1WDIS						1			//BANK 1 Write Disable
.DEFINE	CB_BK0WDIS						0			//BANK 0 Write Disable

// P_Flash_Cmd register //
// word set //
.DEFINE	CW_FlashRW_CMD				0x5A5A			//Flash RW Command
.DEFINE	CW_FlashCMD					0xAAAA			//Flash Command FLash Block
.DEFINE	CW_PageErase				0x5511			//Flash Page Erase Command
.DEFINE	CW_Program					0x5533			//Flash Program Command
.DEFINE	CW_Sequential				0x5544			//Flash Sequential Program Command
.DEFINE	CW_SequentialEnd			0xFFFF			//Flash Sequential Program End Command

// P_IOA_SPE register //
// word set //
.DEFINE CW_IOA_TMR2_TGRA_SFR_EN		0x0200			//TGRA of Timer2 special function enable
.DEFINE CW_IOA_TMR2_TGRB_SFR_EN		0x0400			//TGRB of Timer2 special function enable
.DEFINE CW_IOA_TCLKA_SFR_EN			0x0800			//External clock A input enable
.DEFINE CW_IOA_TCLKB_SFR_EN			0x1000			//External clock B input enable
.DEFINE CW_IOA_TCLKC_SFR_EN			0x2000			//External clock C input enable
.DEFINE CW_IOA_TCLKD_SFREN			0x4000			//External clock D input enable

// Bit set //
.DEFINE CB_IOA_TMR2_TGRA_SFR_EN			9			//TGRA of Timer2 special function enable
.DEFINE CB_IOA_TMR2_TGRB_SFR_EN			10			//TGRB of Timer2 special function enable
.DEFINE CB_IOA_TCLKA_SFR_EN				11			//External clock A input enable
.DEFINE CB_IOA_TCLKB_SFR_EN				12			//External clock B input enable
.DEFINE CB_IOA_TCLKC_SFR_EN				13			//External clock C input enable
.DEFINE CB_IOA_TCLKD_SFREN				14			//External clock D input enable

// P_IOA_KCER register //
// word set //
.DEFINE CW_IOA_KC8_EN				0x0100			//IOA8 key change enable
.DEFINE CW_IOA_KC9_EN				0x0200			//IOA9 key change enable
.DEFINE CW_IOA_KC10_EN				0x0400			//IOA10 key change enable
.DEFINE CW_IOA_KC11_EN				0x0800			//IOA11 key change enable
.DEFINE CW_IOA_KC12_EN				0x1000			//IOA12 key change enable
.DEFINE CW_IOA_KC13_EN				0x2000			//IOA13 key change enable
.DEFINE CW_IOA_KC14_EN				0x4000			//IOA14 key change enable
.DEFINE CW_IOA_KC15_EN				0x8000			//IOA15 key change enable

// Bit set //
.DEFINE CB_IOA_KC8_EN					8			//IOA8 key change enable
.DEFINE CB_IOA_KC9_EN					9			//IOA9 key change enable
.DEFINE CB_IOA_KC10_EN					10			//IOA10 key change enable
.DEFINE CB_IOA_KC11_EN					11			//IOA11 key change enable
.DEFINE CB_IOA_KC12_EN					12			//IOA12 key change enable
.DEFINE CB_IOA_KC13_EN					13			//IOA13 key change enable
.DEFINE CB_IOA_KC14_EN					14			//IOA14 key change enable
.DEFINE CB_IOA_KC15_EN					15			//IOA15 key change enable

// P_IOB_SPE register //
// word set //
.DEFINE CW_IOB_W1N_SFR_EN			0x0001			//IOB0 serves as W1N
.DEFINE CW_IOB_V1N_SFR_EN			0x0002			//IOB1 serves as V1N
.DEFINE CW_IOB_U1N_SFR_EN			0x0004			//IOB2 serves as U1N
.DEFINE CW_IOB_W1_SFR_EN			0x0008			//IOB3 serves as W1
.DEFINE CW_IOB_V1_SFR_EN			0x0010			//IOB4 serves as V1
.DEFINE CW_IOB_U1_SFR_EN			0x0020			//IOB5 serves as U1
.DEFINE CW_IOB_FTIN1_SFR_EN			0x0040			//IOB6 serves as FTIN1
.DEFINE CW_IOB_OL1_SFR_EN			0x0080			//IOB7 serves as OL1
.DEFINE CW_IOB_TMR0_TGRC_SFR_EN		0x0100			//TGRC of Timer0 special function enable 
.DEFINE CW_IOB_TMR0_TGRB_SFR_EN		0x0200			//TGRB of Timer0 special function enable 
.DEFINE CW_IOB_TMR0_TGRA_SFR_EN		0x0400			//TGRA of Timer0 special function enable 

// Bit set //
.DEFINE CB_IOB_W1N_SFR_EN				0			//IOB0 serves as W1N
.DEFINE CB_IOB_V1N_SFR_EN				1			//IOB1 serves as V1N
.DEFINE CB_IOB_U1N_SFR_EN				2			//IOB2 serves as U1N
.DEFINE CB_IOB_W1_SFR_EN				3			//IOB3 serves as W1
.DEFINE CB_IOB_V1_SFR_EN				4			//IOB4 serves as V1
.DEFINE CB_IOB_U1_SFR_EN				5			//IOB5 serves as U1
.DEFINE CB_IOB_FTIN1_SFR_EN				6			//IOB6 serves as FTIN1
.DEFINE CB_IOB_OL1_SFR_EN				7			//IOB7 serves as OL1
.DEFINE CB_IOB_TMR0_TGRC_SFR_EN			8			//TGRC of Timer0 special function enable 
.DEFINE CB_IOB_TMR0_TGRB_SFR_EN			9			//TGRB of Timer0 special function enable 
.DEFINE CB_IOB_TMR0_TGRA_SFR_EN			10			//TGRA of Timer0 special function enable 

// P_IOC_SPE register //
// word set //
.DEFINE CW_IOC_EXTINT0_SFR_EN		0x0004			//IOC2 external input interrupt 0 enable
.DEFINE CW_IOC_EXTINT1_SFR_EN		0x0008			//IOC3 external input interrupt 0 enable
.DEFINE CW_IOC_TMR1_TGRA_SFR_EN		0x0010			//TGRA of Timer1 special function enable 
.DEFINE CW_IOC_TMR1_TGRB_SFR_EN		0x0020			//TGRB of Timer1 special function enable 
.DEFINE CW_IOC_TMR1_TGRC_SFR_EN		0x0040			//TGRC of Timer1 special function enable 
.DEFINE CW_IOC_OL2_SFR_EN			0x0100			//IOC8 serves as OL2
.DEFINE CW_IOC_FTIN2_SFR_EN			0x0200			//IOC9 serves as FTIN2
.DEFINE CW_IOC_U2_SFR_EN			0x0400			//IOC10 serves as U2
.DEFINE CW_IOC_V2_SFR_EN			0x0800			//IOC11 serves as V2
.DEFINE CW_IOC_W2_SFR_EN			0x1000			//IOC12 serves as W2
.DEFINE CW_IOC_U2N_SFR_EN			0x2000			//IOC13 serves as U2N
.DEFINE CW_IOC_V2N_SFR_EN			0x4000			//IOC14 serves as V2N
.DEFINE CW_IOC_W2N_SFR_EN			0x8000			//IOC15 serves as W2N

// Bit set //
.DEFINE CB_IOC_EXTINT0_SFR_EN			2			//IOC2 external input interrupt 0 enable
.DEFINE CB_IOC_EXTINT1_SFR_EN			3			//IOC3 external input interrupt 0 enable
.DEFINE CB_IOC_TMR1_TGRA_SFR_EN			4			//TGRA of Timer1 special function enable 
.DEFINE CB_IOC_TMR1_TGRB_SFR_EN			5			//TGRB of Timer1 special function enable 
.DEFINE CB_IOC_TMR1_TGRC_SFR_EN			6			//TGRC of Timer1 special function enable 
.DEFINE CB_IOC_OL2_SFR_EN				8			//IOC8 serves as OL2
.DEFINE CB_IOC_FTIN2_SFR_EN				9			//IOC9 serves as FTIN2
.DEFINE CB_IOC_U2_SFR_EN				10			//IOC10 serves as U2
.DEFINE CB_IOC_V2_SFR_EN				11			//IOC11 serves as V2
.DEFINE CB_IOC_W2_SFR_EN				12			//IOC12 serves as W2
.DEFINE CB_IOC_U2N_SFR_EN				13			//IOC13 serves as U2N
.DEFINE CB_IOC_V2N_SFR_EN				14			//IOC14 serves as V2N
.DEFINE CB_IOC_W2N_SFR_EN				15			//IOC15 serves as W2N

//=================================//
// B. Timer0/Timer1/Timer2 register//
//=================================//
// P_TMR0_Ctrl register //
// word set //
.DEFINE CW_TMR0_TMRPS_FCKdiv1			0x0000
.DEFINE CW_TMR0_TMRPS_FCKdiv4			0x0001
.DEFINE CW_TMR0_TMRPS_FCKdiv16			0x0002
.DEFINE CW_TMR0_TMRPS_FCKdiv64			0x0003
.DEFINE CW_TMR0_TMRPS_FCKdiv256			0x0004
.DEFINE CW_TMR0_TMRPS_FCKdiv1024		0x0005
.DEFINE CW_TMR0_TMRPS_TCLKA				0x0006
.DEFINE CW_TMR0_TMRPS_TCLKB				0x0007
.DEFINE CW_TMR0_CKEGS_Rising			(0x0000 << 3)
.DEFINE CW_TMR0_CKEGS_Falling			(0x0001 << 3)
.DEFINE CW_TMR0_CKEGS_Both				(0x0002 << 3)
.DEFINE CW_TMR0_CCLS_Disabled			(0x0000 << 5)
.DEFINE CW_TMR0_CCLS_TGRA				(0x0001 << 5)
.DEFINE CW_TMR0_CCLS_TGRB				(0x0002 << 5)
.DEFINE CW_TMR0_CCLS_TGRC				(0x0003 << 5)
.DEFINE CW_TMR0_CCLS_PDR6				(0x0004 << 5)			
.DEFINE CW_TMR0_CCLS_PDR3				(0x0005	<< 5)		
.DEFINE CW_TMR0_CCLS_PDR				(0x0006 << 5)
.DEFINE CW_TMR0_CCLS_TPR				(0x0007 << 5)
.DEFINE CW_TMR0_CLEGS_NotClear			(0x0000 << 8)
.DEFINE CW_TMR0_CLEGS_Rising			(0x0001 << 8)
.DEFINE CW_TMR0_CLEGS_Falling			(0x0002 << 8)
.DEFINE CW_TMR0_CLEGS_Both				(0x0003 << 8)
.DEFINE CW_TMR0_MODE_Normal				(0x0000 << 10)
.DEFINE CW_TMR0_MODE_Mode1				(0x0004 << 10)
.DEFINE CW_TMR0_MODE_Mode2				(0x0005 << 10)
.DEFINE CW_TMR0_MODE_Mode3				(0x0006 << 10)
.DEFINE CW_TMR0_MODE_Mode4				(0x0007 << 10)
.DEFINE CW_TMR0_MODE_PWM_Edge			(0x0008 << 10)
.DEFINE CW_TMR0_MODE_PWM_Center			(0x000A << 10)
.DEFINE CW_TMR0_SPCK_FCKdiv1			(0x0000 << 14)
.DEFINE CW_TMR0_SPCK_FCKdiv2			(0x0001 << 14)
.DEFINE CW_TMR0_SPCK_FCKdiv4			(0x0002 << 14)
.DEFINE CW_TMR0_SPCK_FCKdiv8			(0x0003 << 14)

// Bit set //
.DEFINE CB_TMR0_TMRPS0					0
.DEFINE CB_TMR0_TMRPS1					1
.DEFINE CB_TMR0_TMRPS2					2
.DEFINE CB_TMR0_CKEGS0					3
.DEFINE CB_TMR0_CKEGS1					4
.DEFINE CB_TMR0_CCLS0					5
.DEFINE CB_TMR0_CCLS1					6
.DEFINE CB_TMR0_CCLS2					7
.DEFINE CB_TMR0_CLEGS0					8
.DEFINE CB_TMR0_CLEGS1					9
.DEFINE CB_TMR0_MODE0					10
.DEFINE CB_TMR0_MODE1					11
.DEFINE CB_TMR0_MODE2					12
.DEFINE CB_TMR0_MODE3					13
.DEFINE CB_TMR0_SPCK0					14
.DEFINE CB_TMR0_SPCK1					15

// P_TMR1_Ctrl register //
// word set //
.DEFINE CW_TMR1_TMRPS_FCKdiv1			0x0000
.DEFINE CW_TMR1_TMRPS_FCKdiv4			0x0001
.DEFINE CW_TMR1_TMRPS_FCKdiv16			0x0002
.DEFINE CW_TMR1_TMRPS_FCKdiv64			0x0003
.DEFINE CW_TMR1_TMRPS_FCKdiv256			0x0004
.DEFINE CW_TMR1_TMRPS_FCKdiv1024		0x0005
.DEFINE CW_TMR1_TMRPS_TCLKA				0x0006
.DEFINE CW_TMR1_TMRPS_TCLKB				0x0007
.DEFINE CW_TMR1_CKEGS_Rising			(0x0000 << 3)
.DEFINE CW_TMR1_CKEGS_Falling			(0x0001 << 3)
.DEFINE CW_TMR1_CKEGS_Both				(0x0002 << 3)
.DEFINE CW_TMR1_CCLS_Disabled			(0x0000 << 5)
.DEFINE CW_TMR1_CCLS_TGRA				(0x0001 << 5)
.DEFINE CW_TMR1_CCLS_TGRB				(0x0002 << 5)
.DEFINE CW_TMR1_CCLS_TGRC				(0x0003 << 5)
.DEFINE CW_TMR1_CCLS_PDR6				(0x0004 << 5)			
.DEFINE CW_TMR1_CCLS_PDR3				(0x0005	<< 5)		
.DEFINE CW_TMR1_CCLS_PDR				(0x0006 << 5)
.DEFINE CW_TMR1_CCLS_TPR				(0x0007 << 5)
.DEFINE CW_TMR1_CLEGS_NotClear			(0x0000 << 8)
.DEFINE CW_TMR1_CLEGS_Rising			(0x0001 << 8)
.DEFINE CW_TMR1_CLEGS_Falling			(0x0002 << 8)
.DEFINE CW_TMR1_CLEGS_Both				(0x0003 << 8)
.DEFINE CW_TMR1_MODE_Normal				(0x0000 << 10)
.DEFINE CW_TMR1_MODE_Mode1				(0x0004 << 10)
.DEFINE CW_TMR1_MODE_Mode2				(0x0005 << 10)
.DEFINE CW_TMR1_MODE_Mode3				(0x0006 << 10)
.DEFINE CW_TMR1_MODE_Mode4				(0x0007 << 10)
.DEFINE CW_TMR1_MODE_PWM_Edge			(0x0008 << 10)
.DEFINE CW_TMR1_MODE_PWM_Center			(0x000A << 10)
.DEFINE CW_TMR1_SPCK_FCKdiv1			(0x0000 << 14)
.DEFINE CW_TMR1_SPCK_FCKdiv2			(0x0001 << 14)
.DEFINE CW_TMR1_SPCK_FCKdiv4			(0x0002 << 14)
.DEFINE CW_TMR1_SPCK_FCKdiv8			(0x0003 << 14)

// Bit set //
.DEFINE CB_TMR1_TMRPS0					0
.DEFINE CB_TMR1_TMRPS1					1
.DEFINE CB_TMR1_TMRPS2					2
.DEFINE CB_TMR1_CKEGS0					3
.DEFINE CB_TMR1_CKEGS1					4
.DEFINE CB_TMR1_CCLS0					5
.DEFINE CB_TMR1_CCLS1					6
.DEFINE CB_TMR1_CCLS2					7
.DEFINE CB_TMR1_CLEGS0					8
.DEFINE CB_TMR1_CLEGS1					9
.DEFINE CB_TMR1_MODE0					10
.DEFINE CB_TMR1_MODE1					11
.DEFINE CB_TMR1_MODE2					12
.DEFINE CB_TMR1_MODE3					13
.DEFINE CB_TMR1_SPCK0					14
.DEFINE CB_TMR1_SPCK1					15

// P_TMR2_Ctrl register //
// word set //
.DEFINE CW_TMR2_TMRPS_FCKdiv1			0x0000
.DEFINE CW_TMR2_TMRPS_FCKdiv4			0x0001
.DEFINE CW_TMR2_TMRPS_FCKdiv16			0x0002
.DEFINE CW_TMR2_TMRPS_FCKdiv64			0x0003
.DEFINE CW_TMR2_TMRPS_FCKdiv256			0x0004
.DEFINE CW_TMR2_TMRPS_FCKdiv1024		0x0005
.DEFINE CW_TMR2_TMRPS_TCLKA				0x0006
.DEFINE CW_TMR2_TMRPS_TCLKB				0x0007
.DEFINE CW_TMR2_CKEGS_Rising			(0x0000 << 3)
.DEFINE CW_TMR2_CKEGS_Falling			(0x0001 << 3)
.DEFINE CW_TMR2_CKEGS_Both				(0x0002 << 3)
.DEFINE CW_TMR2_CCLS_Disabled			(0x0000 << 5)
.DEFINE CW_TMR2_CCLS_TGRA				(0x0001 << 5)
.DEFINE CW_TMR2_CCLS_TGRB				(0x0002 << 5)
.DEFINE CW_TMR2_CCLS_TPR				(0x0007 << 5)
.DEFINE CW_TMR2_CLEGS_NotClear			(0x0000 << 8)
.DEFINE CW_TMR2_CLEGS_Rising			(0x0001 << 8)
.DEFINE CW_TMR2_CLEGS_Falling			(0x0002 << 8)
.DEFINE CW_TMR2_CLEGS_Both				(0x0003 << 8)
.DEFINE CW_TMR2_MODE_Normal				(0x0000 << 10)
.DEFINE CW_TMR2_MODE_PWM_Edge			(0x0008 << 10)
.DEFINE CW_TMR2_MODE_PWM_Center			(0x000A << 10)
.DEFINE CW_TMR2_SPCK_FCKdiv1			(0x0000 << 14)
.DEFINE CW_TMR2_SPCK_FCKdiv2			(0x0001 << 14)
.DEFINE CW_TMR2_SPCK_FCKdiv4			(0x0002 << 14)
.DEFINE CW_TMR2_SPCK_FCKdiv8			(0x0003 << 14)

// Bit set //
.DEFINE CB_TMR2_TMRPS0					0
.DEFINE CB_TMR2_TMRPS1					1
.DEFINE CB_TMR2_TMRPS2					2
.DEFINE CB_TMR2_CKEGS0					3
.DEFINE CB_TMR2_CKEGS1					4
.DEFINE CB_TMR2_CCLS0					5
.DEFINE CB_TMR2_CCLS1					6
.DEFINE CB_TMR2_CCLS2					7
.DEFINE CB_TMR2_CLEGS0					8
.DEFINE CB_TMR2_CLEGS1					9
.DEFINE CB_TMR2_MODE0					10
.DEFINE CB_TMR2_MODE1					11
.DEFINE CB_TMR2_MODE2					12
.DEFINE CB_TMR2_MODE3					13
.DEFINE CB_TMR2_SPCK0					14
.DEFINE CB_TMR2_SPCK1					15

// P_TMR3_Ctrl register //
// word set //
.DEFINE CW_TMR3_TMRPS_FCKdiv1			0x0000