📄 cc1100.lis
字号:
.module cc1100.c
.area data(ram, con, rel)
0000 _rfSettings::
0000 .blkb 1
.area idata
0000 06 .byte 6
.area data(ram, con, rel)
0001 .blkb 1
.area idata
0001 00 .byte 0
.area data(ram, con, rel)
0002 .blkb 1
.area idata
0002 10 .byte 16
.area data(ram, con, rel)
0003 .blkb 1
.area idata
0003 12 .byte 18
.area data(ram, con, rel)
0004 .blkb 1
.area idata
0004 F6 .byte 246
.area data(ram, con, rel)
0005 .blkb 1
.area idata
0005 F5 .byte 245
.area data(ram, con, rel)
0006 .blkb 1
.area idata
0006 75 .byte 117
.area data(ram, con, rel)
0007 .blkb 1
.area idata
0007 03 .byte 3
.area data(ram, con, rel)
0008 .blkb 1
.area idata
0008 20 .byte 32
.area data(ram, con, rel)
0009 .blkb 1
.area idata
0009 E5 .byte 229
.area data(ram, con, rel)
000A .blkb 1
.area idata
000A 00 .byte 0
.area data(ram, con, rel)
000B .blkb 1
.area idata
000B 14 .byte 20
.area data(ram, con, rel)
000C .blkb 1
.area idata
000C 56 .byte 86
.area data(ram, con, rel)
000D .blkb 1
.area idata
000D 00 .byte 0
.area data(ram, con, rel)
000E .blkb 1
.area idata
000E 18 .byte 24
.area data(ram, con, rel)
000F .blkb 1
.area idata
000F 16 .byte 22
.area data(ram, con, rel)
0010 .blkb 1
.area idata
0010 6C .byte 108
.area data(ram, con, rel)
0011 .blkb 1
.area idata
0011 03 .byte 3
.area data(ram, con, rel)
0012 .blkb 1
.area idata
0012 40 .byte 64
.area data(ram, con, rel)
0013 .blkb 1
.area idata
0013 91 .byte 145
.area data(ram, con, rel)
0014 .blkb 1
.area idata
0014 E9 .byte 233
.area data(ram, con, rel)
0015 .blkb 1
.area idata
0015 0A .byte 10
.area data(ram, con, rel)
0016 .blkb 1
.area idata
0016 20 .byte 32
.area data(ram, con, rel)
0017 .blkb 1
.area idata
0017 0D .byte 13
.area data(ram, con, rel)
0018 .blkb 1
.area idata
0018 59 .byte 89
.area data(ram, con, rel)
0019 .blkb 1
.area idata
0019 81 .byte 129
.area data(ram, con, rel)
001A .blkb 1
.area idata
001A 35 .byte 53
.area data(ram, con, rel)
001B .blkb 1
.area idata
001B 09 .byte 9
.area data(ram, con, rel)
001C .blkb 1
.area idata
001C 00 .byte 0
.area data(ram, con, rel)
001D .dbfile H:\work\myWork\AVR-CC1100\cc1100.c
001D .dbstruct 0 29 S_RF_SETTINGS
001D .dbfield 0 FSCTRL1 c
001D .dbfield 1 FSCTRL0 c
001D .dbfield 2 FREQ2 c
001D .dbfield 3 FREQ1 c
001D .dbfield 4 FREQ0 c
001D .dbfield 5 MDMCFG4 c
001D .dbfield 6 MDMCFG3 c
001D .dbfield 7 MDMCFG2 c
001D .dbfield 8 MDMCFG1 c
001D .dbfield 9 MDMCFG0 c
001D .dbfield 10 CHANNR c
001D .dbfield 11 DEVIATN c
001D .dbfield 12 FREND1 c
001D .dbfield 13 FREND0 c
001D .dbfield 14 MCSM0 c
001D .dbfield 15 FOCCFG c
001D .dbfield 16 BSCFG c
001D .dbfield 17 AGCCTRL2 c
001D .dbfield 18 AGCCTRL1 c
001D .dbfield 19 AGCCTRL0 c
001D .dbfield 20 FSCAL3 c
001D .dbfield 21 FSCAL2 c
001D .dbfield 22 FSCAL1 c
001D .dbfield 23 FSCAL0 c
001D .dbfield 24 FSTEST c
001D .dbfield 25 TEST2 c
001D .dbfield 26 TEST1 c
001D .dbfield 27 TEST0 c
001D .dbfield 28 IOCFG2 c
001D .dbend
001D .dbsym e rfSettings _rfSettings S[S_RF_SETTINGS]
001D _paTable::
001D .blkb 2
.area idata
001D C000 .byte 192,0
.area data(ram, con, rel)
001F .dbfile H:\work\myWork\AVR-CC1100\cc1100.c
001F .blkb 2
.area idata
001F 0000 .byte 0,0
.area data(ram, con, rel)
0021 .dbfile H:\work\myWork\AVR-CC1100\cc1100.c
0021 .blkb 2
.area idata
0021 0000 .byte 0,0
.area data(ram, con, rel)
0023 .dbfile H:\work\myWork\AVR-CC1100\cc1100.c
0023 .blkb 2
.area idata
0023 0000 .byte 0,0
.area data(ram, con, rel)
0025 .dbfile H:\work\myWork\AVR-CC1100\cc1100.c
0025 .dbsym e paTable _paTable A[8:8]c
.area text(rom, con, rel)
0000 .dbfile H:\work\myWork\AVR-CC1100\cc1100.c
0000 .dbfunc e Wait _Wait fV
0000 ; timeout -> R16
.even
0000 _Wait::
0000 .dbline -1
0000 .dbline 51
0000 ; /*
0000 ; * 文件名：cc1100.c
0000 ; * 功能 : cc1100 的功能实现函数
0000 ; * author: 陈思
0000 ; */
0000 ;
0000 ; #include "cc1100.h"
0000 ;
0000 ;
0000 ; extern ChipState fCC1100;
0000 ;
0000 ; RF_SETTINGS rfSettings = {
0000 ;
0000 ; 0x06, // FSCTRL1 Frequency synthesizer control.
0000 ; 0x00, // FSCTRL0 Frequency synthesizer control.
0000 ; 0x10, // FREQ2 Frequency control word, high byte.
0000 ; 0x12, // FREQ1 434MHz
0000 ; 0xF6, // FREQ0 434MHz
0000 ; // 0x09, // FREQ1 433MHz
0000 ; // 0x7B, // FREQ0 433MHz
0000 ; 0xF5, // MDMCFG4 Modem configuration.
0000 ; 0x75, // MDMCFG3 Modem configuration.
0000 ; 0x03, // MDMCFG2 Modem configuration.
0000 ; 0x20, // MDMCFG1 Modem configuration. oooooooooooooooooo
0000 ; 0xE5, // MDMCFG0 Modem configuration.
0000 ; 0x00, // CHANNR Channel number.
0000 ; 0x14, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0000 ; 0x56, // FREND1 Front end RX configuration.
0000 ; 0x00, // FREND0 Front end RX configuration.
0000 ; 0x18, // MCSM0 Main Radio Control State Machine configuration.
0000 ; 0x16, // FOCCFG Frequency Offset Compensation Configuration.
0000 ; 0x6C, // BSCFG Bit synchronization Configuration.
0000 ; 0x03, // AGCCTRL2 AGC control.
0000 ; 0x40, // AGCCTRL1 AGC control.
0000 ; 0x91, // AGCCTRL0 AGC control.
0000 ; 0xE9, // FSCAL3 Frequency synthesizer calibration.
0000 ; 0x0A, // FSCAL2 Frequency synthesizer calibration.
0000 ; 0x20, // FSCAL1 Frequency synthesizer calibration.
0000 ; 0x0D, // FSCAL0 Frequency synthesizer calibration.
0000 ; 0x59, // FSTEST Frequency synthesizer calibration.
0000 ; 0x81, // TEST2 Various test settings.
0000 ; 0x35, // TEST1 Various test settings.
0000 ; 0x09, // TEST0 Various test settings.
0000 ;
0000 ; };
0000 ;
0000 ; // 发射功率相关定义
0000 ; BYTE paTable[] = {0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
0000 ;
0000 ; void Wait(BYTE timeout)
0000 ; {
0000 L2:
0000 .dbline 53
0000 ; // This sequence uses exactly 2 clock cycle for each round
0000 ; do {
0000 .dbline 54
0000 ; NOP();
0000 0000 nop
0002 .dbline 56
0002 L3:
0002 .dbline 56
0002 ;
0002 ; } while (--timeout);
0002 802F mov R24,R16
0004 8150 subi R24,1
0006 082F mov R16,R24
0008 8823 tst R24
000A D1F7 brne L2
000C .dbline -2
000C L1:
000C .dbline 0 ; func end
000C 0895 ret
000E .dbsym r timeout 16 c
000E .dbend
000E .dbfunc e resetCC1100 _resetCC1100 fV
.even
000E _resetCC1100::
000E .dbline -1
000E .dbline 61
000E ;
000E ; }
000E ;
000E ; void resetCC1100(void)
000E ; {
000E .dbline 63
000E ;
000E ; PORT_SPI &= 1<<SCLK;
000E 85B1 in R24,0x5
0010 8072 andi R24,32
0012 85B9 out 0x5,R24
0014 .dbline 64
0014 ; PORT_SPI &= ~(1<<MOSI);
0014 2B98 cbi 0x5,3
0016 .dbline 65
0016 ; SPI_OFF();
0016 2A9A sbi 0x5,2
0018 .dbline 66
0018 ; Wait(2);
0018 02E0 ldi R16,2
001A F2DF rcall _Wait
001C .dbline 67
001C ; SPI_ON();
001C 2A98 cbi 0x5,2
001E .dbline 68
001E ; Wait(2);
001E 02E0 ldi R16,2
0020 EFDF rcall _Wait
0022 .dbline 69
0022 ; SPI_OFF();
0022 2A9A sbi 0x5,2
0024 .dbline 70
0024 ; Wait(20);
0024 04E1 ldi R16,20
0026 ECDF rcall _Wait
0028 .dbline 71
0028 ; SPI_ON();
0028 2A98 cbi 0x5,2
002A L6:
002A .dbline 73
002A L7:
002A .dbline 73
002A ;
002A ; while ((PORT_SPI & 1<<MISO));
002A 2C99 sbic 0x5,4
002C FECF rjmp L6
002E L9:
002E .dbline 74
002E .dbline 74
002E 80E3 ldi R24,48
0030 8EBD out 0x2e,R24
0032 .dbline 74
0032 L15:
0032 .dbline 74
0032 L16:
0032 .dbline 74
0032 ; SPI_TX(CC1100_SRES);
0032 2DB4 in R2,0x2d
0034 27FE sbrs R2,7
0036 FDCF rjmp L15
0038 .dbline 74
0038 .dbline 74
0038 .dbline 74
0038 .dbline 74
0038 .dbline 75
0038 L21:
0038 .dbline 75
0038 L22:
0038 .dbline 75
0038 ; SPI_WAIT();
0038 2DB4 in R2,0x2d
003A 27FE sbrs R2,7
003C FDCF rjmp L21
003E .dbline 75
003E .dbline 75
003E L24:
003E .dbline 76
003E L25:
003E .dbline 76
003E ; while ((PORT_SPI & 1<<MISO));
003E 2C99 sbic 0x5,4
0040 FECF rjmp L24
0042 .dbline 77
0042 ; SPI_OFF();
0042 2A9A sbi 0x5,2
0044 .dbline 79
0044 ;
0044 ; fCC1100 = IDLE;
0044 2224 clr R2
0046 20920000 sts _fCC1100,R2
004A .dbline -2
004A L5:
004A .dbline 0 ; func end
004A 0895 ret
004C .dbend
004C .dbfunc e cc1100Init _cc1100Init fV
.even
004C _cc1100Init::
004C .dbline -1
004C .dbline 85
004C ;
004C ; }
004C ;
004C ; // CC1100初始化和寄存器配置
004C ; void cc1100Init()
004C ; {
004C .dbline 86
004C ; resetCC1100();
004C E0DF rcall _resetCC1100
004E .dbline 87
004E ; spiWriteRfSettings();
004E 85D0 rcall _spiWriteRfSettings
0050 .dbline -2
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