📄 avrcc1100.lst
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__start:
__text_start:
002D EFCF LDI R28,0xFF
002E E0D4 LDI R29,4
002F BFCD OUT 0x3D,R28
0030 BFDE OUT 0x3E,R29
0031 51C0 SUBI R28,0x10
0032 40D0 SBCI R29,0
0033 EA0A LDI R16,0xAA
0034 8308 STD Y+0,R16
0035 2400 CLR R0
0036 E2E6 LDI R30,0x26
0037 E0F1 LDI R31,1
0038 E012 LDI R17,2
0039 32E7 CPI R30,0x27
003A 07F1 CPC R31,R17
003B F011 BEQ 0x003E
003C 9201 ST R0,Z+
003D CFFB RJMP 0x0039
003E 8300 STD Z+0,R16
003F E3E4 LDI R30,0x34
0040 E0F0 LDI R31,0
0041 E0A0 LDI R26,0
0042 E0B1 LDI R27,1
0043 E010 LDI R17,0
0044 35EA CPI R30,0x5A
0045 07F1 CPC R31,R17
0046 F021 BEQ 0x004B
0047 95C8 LPM
0048 9631 ADIW R30,1
0049 920D ST R0,X+
004A CFF9 RJMP 0x0044
004B D278 RCALL _main
_exit:
004C CFFF RJMP _exit
FILE: H:\work\myWork\AVR-CC1100\cc1100.c
(0001) /*
(0002) * 文件名：cc1100.c
(0003) * 功能 : cc1100 的功能实现函数
(0004) * author: 陈思
(0005) */
(0006)
(0007) #include "cc1100.h"
(0008)
(0009)
(0010) extern ChipState fCC1100;
(0011)
(0012) RF_SETTINGS rfSettings = {
(0013)
(0014) 0x06, // FSCTRL1 Frequency synthesizer control.
(0015) 0x00, // FSCTRL0 Frequency synthesizer control.
(0016) 0x10, // FREQ2 Frequency control word, high byte.
(0017) 0x12, // FREQ1 434MHz
(0018) 0xF6, // FREQ0 434MHz
(0019) // 0x09, // FREQ1 433MHz
(0020) // 0x7B, // FREQ0 433MHz
(0021) 0xF5, // MDMCFG4 Modem configuration.
(0022) 0x75, // MDMCFG3 Modem configuration.
(0023) 0x03, // MDMCFG2 Modem configuration.
(0024) 0x20, // MDMCFG1 Modem configuration. oooooooooooooooooo
(0025) 0xE5, // MDMCFG0 Modem configuration.
(0026) 0x00, // CHANNR Channel number.
(0027) 0x14, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
(0028) 0x56, // FREND1 Front end RX configuration.
(0029) 0x00, // FREND0 Front end RX configuration.
(0030) 0x18, // MCSM0 Main Radio Control State Machine configuration.
(0031) 0x16, // FOCCFG Frequency Offset Compensation Configuration.
(0032) 0x6C, // BSCFG Bit synchronization Configuration.
(0033) 0x03, // AGCCTRL2 AGC control.
(0034) 0x40, // AGCCTRL1 AGC control.
(0035) 0x91, // AGCCTRL0 AGC control.
(0036) 0xE9, // FSCAL3 Frequency synthesizer calibration.
(0037) 0x0A, // FSCAL2 Frequency synthesizer calibration.
(0038) 0x20, // FSCAL1 Frequency synthesizer calibration.
(0039) 0x0D, // FSCAL0 Frequency synthesizer calibration.
(0040) 0x59, // FSTEST Frequency synthesizer calibration.
(0041) 0x81, // TEST2 Various test settings.
(0042) 0x35, // TEST1 Various test settings.
(0043) 0x09, // TEST0 Various test settings.
(0044)
(0045) };
(0046)
(0047) // 发射功率相关定义
(0048) BYTE paTable[] = {0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
(0049)
(0050) void Wait(BYTE timeout)
(0051) {
(0052) // This sequence uses exactly 2 clock cycle for each round
(0053) do {
(0054) NOP();
_Wait:
timeout --> R16
004D 0000 NOP
(0055)
(0056) } while (--timeout);
004E 2F80 MOV R24,R16
004F 5081 SUBI R24,1
0050 2F08 MOV R16,R24
0051 2388 TST R24
0052 F7D1 BNE 0x004D
0053 9508 RET
(0057)
(0058) }
(0059)
(0060) void resetCC1100(void)
(0061) {
(0062)
(0063) PORT_SPI &= 1<<SCLK;
_resetCC1100:
0054 B185 IN R24,0x05
0055 7280 ANDI R24,0x20
0056 B985 OUT 0x05,R24
(0064) PORT_SPI &= ~(1<<MOSI);
0057 982B CBI 0x05,3
(0065) SPI_OFF();
0058 9A2A SBI 0x05,2
(0066) Wait(2);
0059 E002 LDI R16,2
005A DFF2 RCALL _Wait
(0067) SPI_ON();
005B 982A CBI 0x05,2
(0068) Wait(2);
005C E002 LDI R16,2
005D DFEF RCALL _Wait
(0069) SPI_OFF();
005E 9A2A SBI 0x05,2
(0070) Wait(20);
005F E104 LDI R16,0x14
0060 DFEC RCALL _Wait
(0071) SPI_ON();
0061 982A CBI 0x05,2
(0072)
(0073) while ((PORT_SPI & 1<<MISO));
0062 992C SBIC 0x05,4
0063 CFFE RJMP 0x0062
(0074) SPI_TX(CC1100_SRES);
0064 E380 LDI R24,0x30
0065 BD8E OUT 0x2E,R24
0066 B42D IN R2,0x2D
0067 FE27 SBRS R2,7
0068 CFFD RJMP 0x0066
(0075) SPI_WAIT();
0069 B42D IN R2,0x2D
006A FE27 SBRS R2,7
006B CFFD RJMP 0x0069
(0076) while ((PORT_SPI & 1<<MISO));
006C 992C SBIC 0x05,4
006D CFFE RJMP 0x006C
(0077) SPI_OFF();
006E 9A2A SBI 0x05,2
(0078)
(0079) fCC1100 = IDLE;
006F 2422 CLR R2
0070 92200225 STS fCC1100,R2
0072 9508 RET
(0080)
(0081) }
(0082)
(0083) // CC1100初始化和寄存器配置
(0084) void cc1100Init()
(0085) {
(0086) resetCC1100();
_cc1100Init:
0073 DFE0 RCALL _resetCC1100
(0087) spiWriteRfSettings();
0074 D085 RCALL _spiWriteRfSettings
0075 9508 RET
_spiReadReg:
x --> R20
addr --> R16
0076 D28F RCALL push_gset1
(0088)
(0089)
(0090) }
(0091)
(0092) BYTE spiReadReg(BYTE addr)
(0093) {
(0094) UINT8 x;
(0095) SPI_ON();
0077 982A CBI 0x05,2
(0096)
(0097) while((PORT_SPI & 1<<MISO));
0078 992C SBIC 0x05,4
0079 CFFE RJMP 0x0078
(0098) NOP();
007A 0000 NOP
(0099) SPI_TX(addr | READ_SINGLE);
007B 2F80 MOV R24,R16
007C 6880 ORI R24,0x80
007D BD8E OUT 0x2E,R24
007E B42D IN R2,0x2D
007F FE27 SBRS R2,7
0080 CFFD RJMP 0x007E
(0100) SPI_RX(x);
0081 2422 CLR R2
0082 BC2E OUT 0x2E,R2
0083 B42D IN R2,0x2D
0084 FE27 SBRS R2,7
0085 CFFD RJMP 0x0083
0086 B54E IN R20,0x2E
(0101)
(0102) SPI_OFF();
0087 9A2A SBI 0x05,2
(0103) return x;
0088 2F04 MOV R16,R20
0089 D27F RCALL pop_gset1
008A 9508 RET
_spiReadStatus:
x --> R20
addr --> R16
008B D27A RCALL push_gset1
(0104) }
(0105)
(0106) BYTE spiReadStatus(BYTE addr)
(0107) {
(0108) UINT8 x;
(0109)
(0110) SPI_ON();
008C 982A CBI 0x05,2
(0111) NOP();
008D 0000 NOP
(0112) while(PORT_SPI&1<<MISO);
008E 992C SBIC 0x05,4
008F CFFE RJMP 0x008E
(0113) NOP();
0090 0000 NOP
(0114) SPI_TX(addr | READ_BURST);
0091 2F80 MOV R24,R16
0092 6C80 ORI R24,0xC0
0093 BD8E OUT 0x2E,R24
0094 B42D IN R2,0x2D
0095 FE27 SBRS R2,7
0096 CFFD RJMP 0x0094
(0115) SPI_RX(x);
0097 2422 CLR R2
0098 BC2E OUT 0x2E,R2
0099 B42D IN R2,0x2D
009A FE27 SBRS R2,7
009B CFFD RJMP 0x0099
009C B54E IN R20,0x2E
(0116) NOP();
009D 0000 NOP
(0117) SPI_OFF();
009E 9A2A SBI 0x05,2
(0118) return x;
009F 2F04 MOV R16,R20
00A0 D268 RCALL pop_gset1
00A1 9508 RET
_spiReadBurstReg:
i --> R20
count --> R22
buffer --> R18
addr --> R16
00A2 D261 RCALL push_gset2
00A3 816C LDD R22,Y+4
(0119) }
(0120)
(0121) void spiReadBurstReg(BYTE addr, BYTE *buffer, BYTE count)
(0122) {
(0123) UINT8 i;
(0124) SPI_ON();
00A4 982A CBI 0x05,2
(0125) while(PORT_SPI&1<<MISO);
00A5 992C SBIC 0x05,4
00A6 CFFE RJMP 0x00A5
(0126) NOP();
00A7 0000 NOP
(0127) SPI_TX(addr | READ_BURST);
00A8 2F80 MOV R24,R16
00A9 6C80 ORI R24,0xC0
00AA BD8E OUT 0x2E,R24
00AB B42D IN R2,0x2D
00AC FE27 SBRS R2,7
00AD CFFD RJMP 0x00AB
(0128) for (i = 0; i < count; i++)
00AE 2744 CLR R20
00AF C00C RJMP 0x00BC
(0129) {
(0130) SPI_RX(buffer[i]);
00B0 2422 CLR R2
00B1 BC2E OUT 0x2E,R2
00B2 B42D IN R2,0x2D
00B3 FE27 SBRS R2,7
00B4 CFFD RJMP 0x00B2
00B5 2FE4 MOV R30,R20
00B6 27FF CLR R31
00B7 0FE2 ADD R30,R18
00B8 1FF3 ADC R31,R19
00B9 B42E IN R2,0x2E
00BA 8220 STD Z+0,R2
00BB 9543 INC R20
00BC 1746 CP R20,R22
00BD F390 BCS 0x00B0
(0131) }
(0132) NOP();
00BE 0000 NOP
(0133) SPI_OFF();
00BF 9A2A SBI 0x05,2
00C0 D239 RCALL pop_gset2
00C1 9508 RET
(0134) //buffer[i] = 0; // add a terminal char
(0135) }
(0136)
(0137) void spiStrobe(BYTE strobe)
(0138) {
(0139)
(0140) SPI_ON();
_spiStrobe:
strobe --> R16
00C2 982A CBI 0x05,2
(0141) NOP();
00C3 0000 NOP
(0142) while(PORT_SPI&1<<MISO);
00C4 992C SBIC 0x05,4
00C5 CFFE RJMP 0x00C4
(0143) NOP();
00C6 0000 NOP
(0144) SPI_TX(strobe);
00C7 BD0E OUT 0x2E,R16
00C8 B42D IN R2,0x2D
00C9 FE27 SBRS R2,7
00CA CFFD RJMP 0x00C8
(0145) NOP();
00CB 0000 NOP
(0146) SPI_OFF();
00CC 9A2A SBI 0x05,2
00CD 9508 RET
(0147) }
(0148)
(0149) void spiWriteReg(BYTE addr, BYTE value)
(0150) {
(0151) SPI_ON();
_spiWriteReg:
value --> R18
addr --> R16
00CE 982A CBI 0x05,2
(0152) NOP();
00CF 0000 NOP
(0153) while(PORT_SPI&1<<MISO);
00D0 992C SBIC 0x05,4
00D1 CFFE RJMP 0x00D0
(0154) NOP();
00D2 0000 NOP
(0155) SPI_TX(addr);
00D3 BD0E OUT 0x2E,R16
00D4 B42D IN R2,0x2D
00D5 FE27 SBRS R2,7
00D6 CFFD RJMP 0x00D4
(0156) SPI_TX(value);
00D7 BD2E OUT 0x2E,R18
00D8 B42D IN R2,0x2D
00D9 FE27 SBRS R2,7
00DA CFFD RJMP 0x00D8
(0157) NOP();
00DB 0000 NOP
(0158) SPI_OFF();
00DC 9A2A SBI 0x05,2
00DD 9508 RET
_spiWriteBurstReg:
i --> R20
count --> R22
buffer --> R18
addr --> R16
00DE D225 RCALL push_gset2
00DF 816C LDD R22,Y+4
(0159) }
(0160)
(0161) void spiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count)
(0162) {
(0163) UINT8 i;
(0164) SPI_ON();
00E0 982A CBI 0x05,2
(0165) while((PORT_SPI&1<<MISO));
00E1 992C SBIC 0x05,4
00E2 CFFE RJMP 0x00E1
(0166) SPI_TX(addr | WRITE_BURST);
00E3 2F80 MOV R24,R16
00E4 6480 ORI R24,0x40
00E5 BD8E OUT 0x2E,R24
00E6 B42D IN R2,0x2D
00E7 FE27 SBRS R2,7
00E8 CFFD RJMP 0x00E6
(0167) for (i = 0; i < count; i++)
00E9 2744 CLR R20
00EA C00A RJMP 0x00F5
(0168) {
(0169) SPI_TX(buffer[i]);
00EB 2FE4 MOV R30,R20
00EC 27FF CLR R31
00ED 0FE2 ADD R30,R18
00EE 1FF3 ADC R31,R19
00EF 8020 LDD R2,Z+0
00F0 BC2E OUT 0x2E,R2
00F1 B42D IN R2,0x2D
00F2 FE27 SBRS R2,7
00F3 CFFD RJMP 0x00F1
00F4 9543 INC R20
00F5 1746 CP R20,R22
00F6 F3A0 BCS 0x00EB
(0170) }
(0171) SPI_OFF();
00F7 9A2A SBI 0x05,2
00F8 D201 RCALL pop_gset2
00F9 9508 RET
_spiWriteRfSettings:
00FA 9721 SBIW R28,1
(0172) }
(0173)
(0174)
(0175)
(0176)
(0177)
(0178) void spiWriteRfSettings()
(0179) {
(0180)
(0181) // Write register settings
(0182)
(0183) spiWriteReg(CC1100_FSCTRL1, rfSettings.FSCTRL1);
00FB 91200100 LDS R18,rfSettings
00FD E00B LDI R16,0xB
00FE DFCF RCALL _spiWriteReg
(0184) spiWriteReg(CC1100_FSCTRL0, rfSettings.FSCTRL0);
00FF 91200101 LDS R18,rfSettings+1
0101 E00C LDI R16,0xC
0102 DFCB RCALL _spiWriteReg
(0185) spiWriteReg(CC1100_FREQ2, rfSettings.FREQ2);
0103 91200102 LDS R18,rfSettings+2
0105 E00D LDI R16,0xD
0106 DFC7 RCALL _spiWriteReg
(0186) spiWriteReg(CC1100_FREQ1, rfSettings.FREQ1);
0107 91200103 LDS R18,rfSettings+3
0109 E00E LDI R16,0xE
010A DFC3 RCALL _spiWriteReg
(0187) spiWriteReg(CC1100_FREQ0, rfSettings.FREQ0);
010B 91200104 LDS R18,0x104
010D E00F LDI R16,0xF
010E DFBF RCALL _spiWriteReg
(0188) spiWriteReg(CC1100_MDMCFG4, rfSettings.MDMCFG4);
010F 91200105 LDS R18,0x105
0111 E100 LDI R16,0x10
0112 DFBB RCALL _spiWriteReg
(0189) spiWriteReg(CC1100_MDMCFG3, rfSettings.MDMCFG3);
0113 91200106 LDS R18,0x106
0115 E101 LDI R16,0x11
0116 DFB7 RCALL _spiWriteReg
(0190) spiWriteReg(CC1100_MDMCFG2, rfSettings.MDMCFG2);
0117 91200107 LDS R18,0x107
0119 E102 LDI R16,0x12
011A DFB3 RCALL _spiWriteReg
(0191) spiWriteReg(CC1100_MDMCFG1, rfSettings.MDMCFG1);
011B 91200108 LDS R18,0x108
011D E103 LDI R16,0x13
011E DFAF RCALL _spiWriteReg
(0192) spiWriteReg(CC1100_MDMCFG0, rfSettings.MDMCFG0);
011F 91200109 LDS R18,0x109
0121 E104 LDI R16,0x14
0122 DFAB RCALL _spiWriteReg
(0193) spiWriteReg(CC1100_CHANNR, rfSettings.CHANNR);
0123 9120010A LDS R18,0x10A
0125 E00A LDI R16,0xA
0126 DFA7 RCALL _spiWriteReg
(0194) spiWriteReg(CC1100_DEVIATN, rfSettings.DEVIATN);
0127 9120010B LDS R18,0x10B
0129 E105 LDI R16,0x15
012A DFA3 RCALL _spiWriteReg
(0195) spiWriteReg(CC1100_FREND1, rfSettings.FREND1);
012B 9120010C LDS R18,0x10C
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