📄 p18f2431.inc
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LVDL1 EQU H'0001'
LVDL2 EQU H'0002'
LVDL3 EQU H'0003'
LVDEN EQU H'0004'
IRVST EQU H'0005'
IVRST EQU H'0005'
;----- OSCCON Bits -----------------------------------------------------
SCS0 EQU H'0000'
SCS1 EQU H'0001'
FLTS EQU H'0002'
OSTS EQU H'0003'
IRCF0 EQU H'0004'
IRCF1 EQU H'0005'
IRCF2 EQU H'0006'
IDLEN EQU H'0007'
IOFS EQU H'0002'
;----- T0CON Bits -----------------------------------------------------
T0PS0 EQU H'0000'
T0PS1 EQU H'0001'
T0PS2 EQU H'0002'
PSA EQU H'0003'
T0SE EQU H'0004'
T0CS EQU H'0005'
T016BIT EQU H'0006'
TMR0ON EQU H'0007'
T0PS3 EQU H'0003'
;----- STATUS Bits -----------------------------------------------------
C EQU H'0000'
DC EQU H'0001'
Z EQU H'0002'
OV EQU H'0003'
N EQU H'0004'
;----- INTCON3 Bits -----------------------------------------------------
INT1IF EQU H'0000'
INT2IF EQU H'0001'
INT1IE EQU H'0003'
INT2IE EQU H'0004'
INT1IP EQU H'0006'
INT2IP EQU H'0007'
INT1F EQU H'0000'
INT2F EQU H'0001'
INT1E EQU H'0003'
INT2E EQU H'0004'
INT1P EQU H'0006'
INT2P EQU H'0007'
;----- INTCON2 Bits -----------------------------------------------------
RBIP EQU H'0000'
TMR0IP EQU H'0002'
INTEDG2 EQU H'0004'
INTEDG1 EQU H'0005'
INTEDG0 EQU H'0006'
NOT_RBPU EQU H'0007'
T0IP EQU H'0002'
RBPU EQU H'0007'
;----- INTCON Bits -----------------------------------------------------
RBIF EQU H'0000'
INT0IF EQU H'0001'
TMR0IF EQU H'0002'
RBIE EQU H'0003'
INT0IE EQU H'0004'
TMR0IE EQU H'0005'
PEIE EQU H'0006'
GIE EQU H'0007'
INT0F EQU H'0001'
T0IF EQU H'0002'
INT0E EQU H'0004'
T0IE EQU H'0005'
GIEL EQU H'0006'
GIEH EQU H'0007'
;----- STKPTR Bits -----------------------------------------------------
STKPTR0 EQU H'0000'
STKPTR1 EQU H'0001'
STKPTR2 EQU H'0002'
STKPTR3 EQU H'0003'
STKPTR4 EQU H'0004'
STKUNF EQU H'0006'
STKOVF EQU H'0007'
STKFUL EQU H'0007'
;==========================================================================
;
; RAM Definitions
;
;==========================================================================
__MAXRAM H'0FFF'
__BADRAM H'0300'-H'0F5F'
__BADRAM H'0F83'
__BADRAM H'0F85'-H'0F86'
__BADRAM H'0F8C'-H'0F8F'
__BADRAM H'0F95'-H'0F98'
__BADRAM H'0F9C'
__BADRAM H'0FB1'-H'0FB5'
__BADRAM H'0FB9'
__BADRAM H'0FC5'
__BADRAM H'0FD4'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Oscillator Selection:
; OSC = LP LP
; OSC = XT XT
; OSC = HS HS
; OSC = RC2 External RC, RA6 is CLKOUT
; OSC = EC EC, RA6 is CLKOUT
; OSC = ECIO EC, RA6 is I/O
; OSC = HSPLL HS-PLL Enabled
; OSC = RCIO External RC, RA6 is I/O
; OSC = IRCIO Internal RC, RA6 & RA7 are I/O
; OSC = IRC Internal RC, RA6 is CLKOUT, RA7 is I/O
; OSC = RC1 External RC, RA6 is CLKOUT
; OSC = RC External RC, RA6 is CLKOUT
;
; Fail-Safe Clock Monitor Enable:
; FCMEN = OFF Disabled
; FCMEN = ON Enabled
;
; Internal/External Switch-Over:
; IESO = OFF Disabled
; IESO = ON Enabled
;
; Power-up Timer:
; PWRTEN = ON Enabled
; PWRTEN = OFF Disabled
;
; Brown-out Reset:
; BOREN = OFF Disabled
; BOREN = ON Enabled
;
; Brown-out Voltage:
; BORV = 45 4.5V
; BORV = 42 4.2V
; BORV = 27 2.7V
; BORV = 20 2.0V
;
; Watchdog Timer:
; WDTEN = OFF Disabled
; WDTEN = ON Enabled
;
; Watchdog Timer Enable Window:
; WINEN = ON Enabled
; WINEN = OFF Disabled
;
; Watchdog Postscaler:
; WDPS = 1 1:1
; WDPS = 2 1:2
; WDPS = 4 1:4
; WDPS = 8 1:8
; WDPS = 16 1:16
; WDPS = 32 1:32
; WDPS = 64 1:64
; WDPS = 128 1:128
; WDPS = 256 1:256
; WDPS = 512 1:512
; WDPS = 1024 1:1024
; WDPS = 2048 1:2048
; WDPS = 4096 1:4096
; WDPS = 8192 1:8192
; WDPS = 16384 1:16384
; WDPS = 32768 1:32768
;
; Timer1 Oscillator MUX:
; T1OSCMX = OFF Active
; T1OSCMX = ON Inactive
;
; High-Side Transistors Polarity:
; HPOL = LOW Active low
; HPOL = HIGH Active high
;
; Low-Side Transistors Polarity:
; LPOL = LOW Active low
; LPOL = HIGH Active high
;
; PWM output pins Reset state control:
; PWMPIN = ON Enabled
; PWMPIN = OFF Disabled
;
; MCLR Enable:
; MCLRE = OFF Disabled
; MCLRE = ON Enabled
;
; Stack Overflow Reset:
; STVREN = OFF Disabled
; STVREN = ON Enabled
;
; Low Voltage Programming:
; LVP = OFF Disabled
; LVP = ON Enabled
;
; Background Debugger Enable:
; DEBUG = ON Enabled
; DEBUG = OFF Disabled
;
; Code Protection Block 0:
; CP0 = ON Enabled
; CP0 = OFF Disabled
;
; Code Protection Block 1:
; CP1 = ON Enabled
; CP1 = OFF Disabled
;
; Boot Block Code Protection:
; CPB = ON Enabled
; CPB = OFF Disabled
;
; Data EEPROM Code Protection:
; CPD = ON Enabled
; CPD = OFF Disabled
;
; Write Protection Block 0:
; WRT0 = ON Enabled
; WRT0 = OFF Disabled
;
; Write Protection Block 1:
; WRT1 = ON Enabled
; WRT1 = OFF Disabled
;
; Boot Block Write Protection:
; WRTB = ON Enabled
; WRTB = OFF Disabled
;
; Configuration Register Write Protection:
; WRTC = ON Enabled
; WRTC = OFF Disabled
;
; Data EEPROM Write Protection:
; WRTD = ON Enabled
; WRTD = OFF Disabled
;
; Table Read Protection Block 0:
; EBTR0 = ON Enabled
; EBTR0 = OFF Disabled
;
; Table Read Protection Block 1:
; EBTR1 = ON Enabled
; EBTR1 = OFF Disabled
;
; Boot Block Table Read Protection:
; EBTRB = ON Enabled
; EBTRB = OFF Disabled
;
;==========================================================================
;==========================================================================
;
; Configuration Bits
;
; NAME Address
; CONFIG1H 300001h
; CONFIG2L 300002h
; CONFIG2H 300003h
; CONFIG3L 300004h
; CONFIG3H 300005h
; CONFIG4L 300006h
; CONFIG5L 300008h
; CONFIG5H 300009h
; CONFIG6L 30000Ah
; CONFIG6H 30000Bh
; CONFIG7L 30000Ch
; CONFIG7H 30000Dh
;
;==========================================================================
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3L EQU H'300004'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
;----- CONFIG1H Options --------------------------------------------------
_OSC_LP_1H EQU H'F0' ; LP
_OSC_XT_1H EQU H'F1' ; XT
_OSC_HS_1H EQU H'F2' ; HS
_OSC_RC2_1H EQU H'F3' ; External RC, RA6 is CLKOUT
_OSC_EC_1H EQU H'F4' ; EC, RA6 is CLKOUT
_OSC_ECIO_1H EQU H'F5' ; EC, RA6 is I/O
_OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled
_OSC_RCIO_1H EQU H'F7' ; External RC, RA6 is I/O
_OSC_IRCIO_1H EQU H'F8' ; Internal RC, RA6 & RA7 are I/O
_OSC_IRC_1H EQU H'F9' ; Internal RC, RA6 is CLKOUT, RA7 is I/O
_OSC_RC1_1H EQU H'FB' ; External RC, RA6 is CLKOUT
_OSC_RC_1H EQU H'FF' ; External RC, RA6 is CLKOUT
_FCMEN_OFF_1H EQU H'BF' ; Disabled
_FCMEN_ON_1H EQU H'FF' ; Enabled
_IESO_OFF_1H EQU H'7F' ; Disabled
_IESO_ON_1H EQU H'FF' ; Enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRTEN_ON_2L EQU H'FE' ; Enabled
_PWRTEN_OFF_2L EQU H'FF' ; Disabled
_BOREN_OFF_2L EQU H'FD' ; Disabled
_BOREN_ON_2L EQU H'FF' ; Enabled
_BORV_45_2L EQU H'F3' ; 4.5V
_BORV_42_2L EQU H'F7' ; 4.2V
_BORV_27_2L EQU H'FB' ; 2.7V
_BORV_20_2L EQU H'FF' ; 2.0V
;----- CONFIG2H Options --------------------------------------------------
_WDTEN_OFF_2H EQU H'FE' ; Disabled
_WDTEN_ON_2H EQU H'FF' ; Enabled
_WINEN_ON_2H EQU H'DF' ; Enabled
_WINEN_OFF_2H EQU H'FF' ; Disabled
_WDPS_1_2H EQU H'E1' ; 1:1
_WDPS_2_2H EQU H'E3' ; 1:2
_WDPS_4_2H EQU H'E5' ; 1:4
_WDPS_8_2H EQU H'E7' ; 1:8
_WDPS_16_2H EQU H'E9' ; 1:16
_WDPS_32_2H EQU H'EB' ; 1:32
_WDPS_64_2H EQU H'ED' ; 1:64
_WDPS_128_2H EQU H'EF' ; 1:128
_WDPS_256_2H EQU H'F1' ; 1:256
_WDPS_512_2H EQU H'F3' ; 1:512
_WDPS_1024_2H EQU H'F5' ; 1:1024
_WDPS_2048_2H EQU H'F7' ; 1:2048
_WDPS_4096_2H EQU H'F9' ; 1:4096
_WDPS_8192_2H EQU H'FB' ; 1:8192
_WDPS_16384_2H EQU H'FD' ; 1:16384
_WDPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3L Options --------------------------------------------------
_T1OSCMX_OFF_3L EQU H'DF' ; Active
_T1OSCMX_ON_3L EQU H'FF' ; Inactive
_HPOL_LOW_3L EQU H'EF' ; Active low
_HPOL_HIGH_3L EQU H'FF' ; Active high
_LPOL_LOW_3L EQU H'F7' ; Active low
_LPOL_HIGH_3L EQU H'FF' ; Active high
_PWMPIN_ON_3L EQU H'FB' ; Enabled
_PWMPIN_OFF_3L EQU H'FF' ; Disabled
;----- CONFIG3H Options --------------------------------------------------
_MCLRE_OFF_3H EQU H'7F' ; Disabled
_MCLRE_ON_3H EQU H'FF' ; Enabled
;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE' ; Disabled
_STVREN_ON_4L EQU H'FF' ; Enabled
_LVP_OFF_4L EQU H'FB' ; Disabled
_LVP_ON_4L EQU H'FF' ; Enabled
_DEBUG_ON_4L EQU H'7F' ; Enabled
_DEBUG_OFF_4L EQU H'FF' ; Disabled
;----- CONFIG5L Options --------------------------------------------------
_CP0_ON_5L EQU H'FE' ; Enabled
_CP0_OFF_5L EQU H'FF' ; Disabled
_CP1_ON_5L EQU H'FD' ; Enabled
_CP1_OFF_5L EQU H'FF' ; Disabled
;----- CONFIG5H Options --------------------------------------------------
_CPB_ON_5H EQU H'BF' ; Enabled
_CPB_OFF_5H EQU H'FF' ; Disabled
_CPD_ON_5H EQU H'7F' ; Enabled
_CPD_OFF_5H EQU H'FF' ; Disabled
;----- CONFIG6L Options --------------------------------------------------
_WRT0_ON_6L EQU H'FE' ; Enabled
_WRT0_OFF_6L EQU H'FF' ; Disabled
_WRT1_ON_6L EQU H'FD' ; Enabled
_WRT1_OFF_6L EQU H'FF' ; Disabled
;----- CONFIG6H Options --------------------------------------------------
_WRTB_ON_6H EQU H'BF' ; Enabled
_WRTB_OFF_6H EQU H'FF' ; Disabled
_WRTC_ON_6H EQU H'DF' ; Enabled
_WRTC_OFF_6H EQU H'FF' ; Disabled
_WRTD_ON_6H EQU H'7F' ; Enabled
_WRTD_OFF_6H EQU H'FF' ; Disabled
;----- CONFIG7L Options --------------------------------------------------
_EBTR0_ON_7L EQU H'FE' ; Enabled
_EBTR0_OFF_7L EQU H'FF' ; Disabled
_EBTR1_ON_7L EQU H'FD' ; Enabled
_EBTR1_OFF_7L EQU H'FF' ; Disabled
;----- CONFIG7H Options --------------------------------------------------
_EBTRB_ON_7H EQU H'BF' ; Enabled
_EBTRB_OFF_7H EQU H'FF' ; Disabled
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
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