cache.c

T-kernel 的extension源代码

/*
 *----------------------------------------------------------------------
 *    T-Kernel / Standard Extension
 *
 *    Copyright (C) 2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel / Standard Extension is distributed 
 *      under the T-License for T-Kernel / Standard Extension.
 *----------------------------------------------------------------------
 *
 *    Version:   1.00.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/11.
 *
 *----------------------------------------------------------------------
 */

/*
 *	cache.c (memory)
 *
 *	ARM920T-dependent functions
 *
 *	Cache: Write-back system where instruction and data caches are separated
 */

#include "segmgr.h"


#define	CACHE_LINESZ	32U	/* Cache line size (bytes) */

/*
 * Cancel memory cache content (both instruction/data caches)
 *	Cancel (do not write back) a page (4KB) that contains laddr.
 *	Do not specify an invalid page (PTE.p=0).
 *	When set at "lsid = 0", include current space.
 */
EXPORT void InvalidateCache( VP laddr, UW lsid )
{
	VB	*p, *ep;

	if ( isLocalSpace(laddr) != 0 ) {
		/* When not performed in the current unique space, processing is unnecessary. */
		if ( (lsid != 0U) && (GetLSID_tid(TSK_SELF) != lsid) ) {
			return;
		}
	}

	p = PageAlignL(laddr);
	ep = p + PAGESIZE;
	while ( p < ep ) {
		Asm("mcr p15, 0, %0, cr7, c5, 1":: "r"(p));
		Asm("mcr p15, 0, %0, cr7, c6, 1":: "r"(p));
		p += CACHE_LINESZ;
	}
}

/*
 * Flush memory cache (both instruction/data caches)
 *	Flush (write back) a page (4KB) that contains laddr and cancel it.
 *	Do not specify an invalid page (PTE.p=0).
 *	When set at "lsid = 0", include current space.
 */
EXPORT void ExtFlushCacheWB( VP laddr, UW lsid )
{
	VB	*p, *ep;

	if ( isLocalSpace(laddr) != 0 ) {
		/* When not performed in the current unique space, processing is unnecessary. */
		if ( (lsid != 0U) && (GetLSID_tid(TSK_SELF) != lsid) ) {
			return;
		}
	}

	p = PageAlignL(laddr);
	ep = p + PAGESIZE;
	while ( p < ep ) {
		Asm("mcr p15, 0, %0, cr7, c5,  1":: "r"(p));
		Asm("mcr p15, 0, %0, cr7, c14, 1":: "r"(p));
		p += CACHE_LINESZ;
	}
}

/*
 * Write back memory cache (data cache only).
 *	Write back (do not cancel) a page (4KB) that contains laddr.
 *	Do not specify an invalid page (PTE.p=0).
 *	When set at "lsid = 0", include current space.
 */
EXPORT void FlushDCache( VP laddr, UW lsid )
{
	VB	*p, *ep;

	if ( isLocalSpace(laddr) != 0 ) {
		/* When not performed in the current unique space, processing is unnecessary. */
		if ( (lsid != 0U) && (GetLSID_tid(TSK_SELF) != lsid) ) {
			return;
		}
	}

	p = PageAlignL(laddr);
	ep = p + PAGESIZE;
	while ( p < ep ) {
		Asm("mcr p15, 0, %0, cr7, c10, 1":: "r"(p));
		p += CACHE_LINESZ;
	}
}