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📄 cpu_asm.h

📁 T-kernel 的extension源代码
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/* *---------------------------------------------------------------------- *    T-Kernel / Standard Extension * *    Copyright (C) 2006 by Ken Sakamura. All rights reserved. *    T-Kernel / Standard Extension is distributed  *      under the T-License for T-Kernel / Standard Extension. *---------------------------------------------------------------------- * *    Version:   1.00.00 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/11. * *---------------------------------------------------------------------- *//* *	cpu_asm.h (memory) * *	SH7751R-dependent definitions * *	Included from assembler sources. */#ifndef _PM_CPU_ASM_H_#define _PM_CPU_ASM_H_#include <tk/sysdef.h>/* ------------------------------------------------------------------------ *//* *	TLB-related *//* * Page table entry *	The (*) mark is not used in the same manner as in hardware-related definitions. *	When written into TLB, they are changed according to hardware-related *	definitions. */#define	PT_WriteThrough		0x00000001	/* SH4 only */#define	PT_Accessed		0x00000002	/* (*) */#define	PT_Update		0x00000004#define	PT_Cachable		0x00000008#define	PT_Writable		0x00000020#define	PT_User			0x00000040#define	PT_Present		0x00000100#define	PT_Clear		0x00000200	/* (*) */#define	PT_CopyOnWrite		0x00000400	/* (*) */#define	PT_Valid		0x00000800	/* (*) */#define	PT_Address		0xfffff000#define	PTE_NONE		( 0 )		/* Invalid entry *//* * TLB */#define	MMU_Base		0xff000000	/* MMU register base */#define	UTLB_ADR_TOP		0xf6000000	/* UTLB address array */#define	UTLB_DAT_TOP		0xf7000000	/* UTLB data array 1 */#define	UTLB_DAT2_TOP		0xf7800000	/* UTLB data array 2 */#define	UTLB_ENT(n)		( (n) << 8 )	/* n = 0 - 63 */#define	UTLB_A			0x00000080	/* Associative specification */#define	ITLB_ADR_TOP		0xf2000000	/* ITLB address array */#define	ITLB_DAT_TOP		0xf3000000	/* ITLB data array 1 */#define	ITLB_DAT2_TOP		0xf3800000	/* ITLB data array 2 */#define	ITLB_ENT(n)		( (n) << 8 )	/* n = 0 - 3 */#define	TLB_ASID		0x000000ff	/* Logical space ID */#define	TLB_V			0x00000100	/* Valid */#define	TLB_D			0x00000200	/* Dirty */#define	UTLB_MASK		0x1ffff16d	/* UTLB setting value mask */#define	ITLB_MASK		0x1ffff148	/* ITLB setting value mask */#define	TLB_MASK		UTLB_MASK#define	TLB_PageSize4K		0x00000010	/* Specify page size at 4KB */#define	TLB_Share		0x00000002	/* Specify shared state. *//* ------------------------------------------------------------------------ *//* *	Cache-related */#define	CACHE_LINESZ	0x20		/* Cache line size */#define	ICACHE_ADR_TOP	0xf0000000	/* Instruction cache address array */#define	ICACHE_DAT_TOP	0xf1000000	/* Instruction cache data array */#define	ICACHE_WAY_MSK	0x00002000#define	ICACHE_ENT_MSK	0x00001fe0#define	DCACHE_ADR_TOP	0xf4000000	/* Data cache address array */#define	DCACHE_DAT_TOP	0xf5000000	/* Data cache data array */#define	DCACHE_WAY_MSK	0x00004000#define	DCACHE_ENT_MSK	0x00003fe0#define	CACHE_V		0x00000001	/* Valid */#define	CACHE_U		0x00000002	/* Dirty */#define	CACHE_TAG	0xfffffc00	/* Tag */#define	CACHE_A		0x00000008	/* Associative specification *//* ------------------------------------------------------------------------ */#endif

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