cpu_asm.s

T-kernel 的extension源代码

	nop

		.balign	4
  W_PTEH:	.long	PTEH
  W_PTEL:	.long	PTEL
  W_TTB:	.long	TTB
  W_PFAMSK:	.long	PT_Address
  W_TLBMSK:	.long	TLB_MASK

/* ------------------------------------------------------------------------ */

/*
 * Switch logical spaces
 *	UW r2 = changeLogicalSpace( UW r5 = pteh )
 *	For register r5, specify "pteh = lsid".
 *	To register r2, return PTEH before change.
 *	Registers r1, r2 and r5 are destroyed. The other registers are saved.
 */
	.text
	.balign	2
	.type	changeLogicalSpace, @function
changeLogicalSpace:
	mov.l	S_PTEH, r1
	mov.l	@r1, r2			// r2 = Save PTEH before change.
	mov.l	r5, @r1			// Change PTEH

	extu.b	r5, r5
	mov	#NUM_PDIR_ENTRIES_SHIFT + 2, r1
	shld	r1, r5
	mov.l	S_UATB, r1
	mov.l	@r1, r1
	add	r1, r5
	mov.l	S_TTB, r1
	mov.l	r5, @r1			// Change TTB

	rts
	nop

		.balign	4
  S_UATB:	.long	Csym(UATB)
  S_PTEH:	.long	PTEH
  S_TTB:	.long	TTB

/* ------------------------------------------------------------------------ */
/*
 *	Cache-related
 *
 *	In cache control, the program itself needs to be a non-cache area.
 *	Therefore, run the program using a shadow image in P2 area.
 */

/*
 * Flush one page of data cache.
 *	As ope, specify instruction ocbi, ocbp, or ocbwb.
 */
.macro flushDC ope
	mov.l	C_PageSize, r0
	add	r4, r0			// r0 = Page end address
  0:
	add	#-CACHE_LINESZ, r0
	\ope	@r0			// Cache write back
	cmp/hi	r4, r0
	bt	0b
.endm

/*
 * Cancel one page of instruction cache.
 *	void invalidateIC( VP laddr, UW lsid, UW pte )
 *
 *	Laddr must be located at the start of page.
 *	Call in interrupt-disabled state after switching
 *	to a logical space lsid and P2 area.
 *
 *	Destroy registers r0,r1,r6 and r7. Save the other registers.
 */
	.text
	.balign	2
	.type	invalidateIC, @function
invalidateIC:
	tst	r6, r6			// When "pte = PTE_NONE (0)",
	bt	iic_notlb		// do not set for ITLB.

	mov.l	C_ITLB_ADR, r1		// Set for ITLB.
	mov.l	C_TLB_V, r0
	or	r4, r0			// r4 = laddr
	or	r5, r0			// r5 = lsid
	mov.l	r0, @r1			// ITLB ADR = laddr | v | lsid

	mov.l	C_SharedSpace, r7
	mov.l	C_ITLB_DAT1, r1
	mov.l	C_ITLB_MASK, r0
	and	r6, r0			// r6 = pte
	cmp/hs	r7, r4
	bf/s	iic_localspace
	or	#TLB_PageSize4K, r0	// Specify page size (fixed at 4KB).
	or	#TLB_Share, r0		// Specify shared state.
  iic_localspace:
	mov.l	r0, @r1			// ITLB DAT1 = pte

	mov.l	C_ITLB_DAT2, r1
	mov	#0, r0
	mov.l	r0, @r1			// ITLB DAT2 = 0

  iic_notlb:
	mov.l	C_CCR, r1		// Select a cache entry
	mov.l	C_CCR_IIX, r0		// in index mode of
	mov.l	@r1, r1			// instruction cache.
	mov	r4, r7
	tst	r0, r1
	bt	iic_no_iix
	mov	#-(25-12), r0
	shld	r0, r7
  iic_no_iix:
	mov.l	C_ICEntSel, r0
	and	r0, r7

	mov.l	C_ICArray, r0
	mov.l	C_PageSize, r1
	mov.l	C_ICTagMask, r6
	or	r7, r0

  iic_loop:
	add	#-CACHE_LINESZ, r1
	mov	r4, r7			// r4 = laddr
	or	r1, r7			// r1 = ent
	and	r6, r7			// (laddr | ent) & TagMask
	mov.l	r7, @(r0, r1)		// Flush cache
	tst	r1, r1
	bf	iic_loop

	rts
	nop

/*
 * Cancel memory cache content (both instruction/data caches)
 *	void InvalidateCache( VP laddr, UW lsid, UW pte )
 *	Cancel (do not write back) a page (4KB) that contains laddr.
 *	Do not specify an invalid page (PTE.p=0).
 *	Pte is a page table entry in a page of laddr and set for ITLB.
 *	If laddr is not located in TLB mapping area, specify "pte = PTE_NONE".
 */
	.text
	.balign	2
	.globl	Csym(InvalidateCache)
	.type	Csym(InvalidateCache), @function
Csym(InvalidateCache):
	mov	#PT_Writable, r0	// ocbi instruction can be used
	tst	r0, r6			// in writable pages only.
	bf	l_inv_cache		// If pages are not writable,
	tst	r6, r6			// use ExtFlushCache.
	bt	l_inv_cache
	bra	Csym(ExtFlushCache)
	nop

  l_inv_cache:
	sts.l	pr, @-SP

	mov.l	C_PageMask, r0
	and	r0, r4			// r4 = Page start address

	stc	sr, r3			// r3 = SR Save
	mov.l	C_SR_DisInt, r0
	ldc	r0, sr			// Interrupt-disabled

	bsr	changeLogicalSpace	// Switch logical spaces
	nop				// r2 = Save PTEH (logical space ID)

	mov.l	C_GOTO_P2, r0
	braf	r0			// Jump to P2 area.
	nop

	bsr	invalidateIC		// Cancel instruction cache
	nop

	flushDC ocbi			// Cancel data cache

	bsr	changeLogicalSpace	// Turn back logical space.
	mov	r2, r5

	mov.l	C_SR_FD, r0
	or	r0, r3			// SR.FD = 1
	ldc	r3, sr			// Reset interrupt-disabled state (to original state)

	lds.l	@SP+, pr
	rts
	nop

/*
 * Flush memory cache (both instruction/data caches)
 *	void ExtFlushCache( VP laddr, UW lsid, UW pte )
 *	Flush (write back) a page (4KB) that contains laddr and cancel it.
 *	Do not specify an invalid page (PTE.p=0).
 *	Pte is a page table entry in a page of laddr and set for ITLB.
 *	If laddr is not located in TLB mapping area, specify "pte = PTE_NONE".
 */
	.text
	.balign	2
	.globl	Csym(ExtFlushCache)
	.type	Csym(ExtFlushCache), @function
Csym(ExtFlushCache):
	sts.l	pr, @-SP

	mov.l	C_PageMask, r0
	and	r0, r4			// r4 = Page start address

	stc	sr, r3			// r3 = SR Save
	mov.l	C_SR_DisInt, r0
	ldc	r0, sr			// Interrupt-disabled

	bsr	changeLogicalSpace	// Switch logical spaces
	nop				// r2 = Save PTEH (logical space ID)

	mov.l	C_GOTO_P2, r0
	braf	r0			// Jump to P2 area.
	nop

	bsr	invalidateIC		// Cancel instruction cache
	nop
					// Write back data cache
	flushDC ocbp			// and cancel it.

	bsr	changeLogicalSpace	// Turn back logical space.
	mov	r2, r5

	mov.l	C_SR_FD, r0
	or	r0, r3			// SR.FD = 1
	ldc	r3, sr			// Reset interrupt-disabled state (to original state)

	lds.l	@SP+, pr
	rts
	nop

/*
 * Write back memory cache (data cache only).
 *	void FlushDCache( VP laddr, UW lsid )
 *	Write back (do not cancel) a page (4KB) that contains laddr.
 *	Do not specify an invalid page (PTE.p=0).
 */
	.text
	.balign	2
	.globl	Csym(FlushDCache)
	.type	Csym(FlushDCache), @function
Csym(FlushDCache):
	sts.l	pr, @-SP

	mov.l	C_PageMask, r0
	and	r0, r4			// r4 = Page start address

	stc	sr, r3			// r3 = SR Save
	mov.l	C_SR_DisInt, r0
	ldc	r0, sr			// Interrupt-disabled

	bsr	changeLogicalSpace	// Switch logical spaces
	nop				// r2 = Save PTEH (logical space ID)

	mov.l	C_GOTO_P2, r0
	braf	r0			// Jump to P2 area.
	nop

	flushDC ocbwb			// Write back data cache
					// (Do not cancel)

	bsr	changeLogicalSpace	// Turn back logical space.
	mov	r2, r5

	mov.l	C_SR_FD, r0
	or	r0, r3			// SR.FD = 1
	ldc	r3, sr			// Reset interrupt-disabled state (to original state)

	lds.l	@SP+, pr
	rts
	nop

/*
 * Write back memory cache and cancel it (data cache only).
 *	void PurgeDCache( VP laddr, UW lsid )
 *	Write back a page (4KB) that contains laddr and cancel it.
 *	Do not specify an invalid page (PTE.p=0).
 */
	.text
	.balign	2
	.globl	Csym(PurgeDCache)
	.type	Csym(PurgeDCache), @function
Csym(PurgeDCache):
	sts.l	pr, @-SP

	mov.l	C_PageMask, r0
	and	r0, r4			// r4 = Page start address

	stc	sr, r3			// r3 = SR Save
	mov.l	C_SR_DisInt, r0
	ldc	r0, sr			// Interrupt-disabled

	bsr	changeLogicalSpace	// Switch logical spaces
	nop				// r2 = Save PTEH (logical space ID)

	mov.l	C_GOTO_P2, r0
	braf	r0			// Jump to P2 area.
	nop

	flushDC ocbp			// Write back data cache
					// (Cancel)

	bsr	changeLogicalSpace	// Turn back logical space.
	mov	r2, r5

	mov.l	C_SR_FD, r0
	or	r0, r3			// SR.FD = 1
	ldc	r3, sr			// Reset interrupt-disabled state (to original state)

	lds.l	@SP+, pr
	rts
	nop

			.balign	4
  C_ITLB_ADR:		.long	ITLB_ADR_TOP
  C_ITLB_DAT1:		.long	ITLB_DAT_TOP
  C_ITLB_DAT2:		.long	ITLB_DAT2_TOP
  C_ITLB_MASK:		.long	ITLB_MASK
  C_TLB_V:		.long	TLB_V
  C_CCR:		.long	CCR
  C_CCR_IIX:		.long	CCR_IIX
  C_ICArray:		.long	ICACHE_ADR_TOP | CACHE_A
  C_ICEntSel:		.long	ICACHE_ENT_MSK & ~(PAGESIZE-1)
  C_ICTagMask:		.long	CACHE_TAG
  C_PageSize:		.long	PAGESIZE
  C_PageMask:		.long	~(PAGESIZE-1)
  C_SharedSpace:	.long	LOCALSPACE_END
  C_SR_DisInt:		.long	SR_MD | SR_FD | SR_I(15)
  C_SR_FD:		.long	SR_FD
  C_GOTO_P2:		.long	0x20000000

/* ------------------------------------------------------------------------ */
/*
 *	TLB-related
 */

/*
 * Purge the whole TLB
 *	void PurgeAllTLB( void )
 */
	.text
	.balign	2
	.globl	Csym(PurgeAllTLB)
	.type	Csym(PurgeAllTLB), @function
Csym(PurgeAllTLB):
	mov.l	T_MMU_Base, r1		// r1 = MMU register base address

	stc	sr, r3			// r3 = SR Save
	mov.l	T_SR_DisInt, r0
	ldc	r0, sr			// Interrupt-disabled

	mov.l	@(MMUCR - MMU_Base, r1), r0
	or	#MMU_TF, r0
	mov.l	r0, @(MMUCR - MMU_Base, r1)	// MMUCR TF=1

	mov.l	T_SR_FD, r0
	or	r0, r3			// SR.FD = 1
	ldc	r3, sr			// Reset interrupt-disabled state (to original state)

	rts
	nop

/*
 * Purge TLB that contains specified logical address.
 *	void PurgePageTLB( VP laddr, UW lsid )
 */
	.text
	.balign	2
	.globl	Csym(PurgePageTLB)
	.type	Csym(PurgePageTLB), @function
Csym(PurgePageTLB):
	mov.l	T_PageMask, r0
	and	r0, r4			// r4 = Page start address

	mov.l	T_MMU_Base, r1		// r1 = MMU register base address

	stc	sr, r3			// r3 = SR Save
	mov.l	T_SR_DisInt, r0
	ldc	r0, sr			// Interrupt-disabled

	mov.l	@(PTEH - MMU_Base, r1), r2	// r2 = Save PTEH (logical space ID)
	or	r4, r5				// laddr | lsid
	mov.l	r5, @(PTEH - MMU_Base, r1)	// Switch logical spaces

	mov.l	T_GOTO_P2, r0
	braf	r0			// Jump to P2 area.
	nop

	mov.l	T_UTLB_ADR_A, r0
	mov.l	r5, @r0			// TLB purge (V=0 D=0)

	nop;nop;nop;nop;nop;nop;nop

	mov.l	r2, @(PTEH - MMU_Base, r1)	// Turn back logical space.

	mov.l	T_SR_FD, r0
	or	r0, r3			// SR.FD = 1
	ldc	r3, sr			// Reset interrupt-disabled state (to original state)

	rts
	nop

/*
 * Register in TLB
 *	void UpdateTLB( VP laddr, UW lsid, UW pte )
 */
	.text
	.balign	2
	.globl	Csym(UpdateTLB)
	.type	Csym(UpdateTLB), @function
Csym(UpdateTLB):
	mov.l	T_PageMask, r0
	and	r0, r4			// r4 = Page start address

	mov.l	T_MMU_Base, r1		// r1 = MMU register base address

	stc	sr, r3			// r3 = SR Save
	mov.l	T_SR_DisInt, r0
	ldc	r0, sr			// Interrupt-disabled

	mov.l	@(PTEH - MMU_Base, r1), r2	// r2 = Save PTEH (logical space ID)
	or	r4, r5				// laddr | lsid
	mov.l	r5, @(PTEH - MMU_Base, r1)	// Switch logical spaces

	mov.l	T_GOTO_P2, r0
	braf	r0			// Jump to P2 area.
	nop

	mov.l	T_UTLB_ADR_A, r0	// Delete the current registrations.
	mov.l	r5, @r0			// TLB purge (V=0 D=0)

	mov.l	T_SharedSpace, r7
	mov.l	T_UTLB_MASK, r0
	and	r6, r0			// r6 = pte
	cmp/hs	r7, r4
	bf/s	rt_localspace
	or	#TLB_PageSize4K, r0	// Specify page size (fixed at 4KB).
	or	#TLB_Share, r0		// Specify shared state.
  rt_localspace:

	mov	#0, r7
	mov.l	r5, @(PTEH - MMU_Base, r1)	// PTEH = laddr | lsid
	mov.l	r0, @(PTEL - MMU_Base, r1)	// PTEL = pte
	mov.l	r7, @(PTEA - MMU_Base, r1)	// PTEA = 0
	ldtlb					// Register in UTLB
	nop

	mov.l	r2, @(PTEH - MMU_Base, r1)	// Turn back logical space.

	mov.l	T_SR_FD, r0
	or	r0, r3			// SR.FD = 1
	ldc	r3, sr			// Reset interrupt-disabled state (to original state)

	rts
	nop

			.balign	4
  T_UTLB_ADR_A:		.long	UTLB_ADR_TOP | UTLB_A
  T_UTLB_MASK:		.long	UTLB_MASK
  T_PageMask:		.long	~(PAGESIZE-1)
  T_SharedSpace:	.long	LOCALSPACE_END
  T_SR_DisInt:		.long	SR_MD | SR_FD | SR_I(15)
  T_SR_FD:		.long	SR_FD
  T_MMU_Base:		.long	MMU_Base
  T_GOTO_P2:		.long	0x20000000

/* ------------------------------------------------------------------------ */