cpu.h

T-kernel 的extension源代码

/*
 *----------------------------------------------------------------------
 *    T-Kernel / Standard Extension
 *
 *    Copyright (C) 2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel / Standard Extension is distributed 
 *      under the T-License for T-Kernel / Standard Extension.
 *----------------------------------------------------------------------
 *
 *    Version:   1.00.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/11.
 *
 *----------------------------------------------------------------------
 */

/*
 *	cpu.h (memory)
 *
 *	VR4131 (MIPS)-dependent definitions
 *
 *	Physical address space	64GB (36bit)
 *	Minimum page size	4KB
 *
 *	In segment management:
 *	* Supports up to 4GB (32bit) of physical address spaces
 *	* Page size is fixed at 4KB
 */

#ifndef _PM_CPU_H_
#define _PM_CPU_H_

#include <tk/sysdef.h>


/*
 * Page directory entry
 */
typedef union PageDirectryEntry {
	struct pde {
		unsigned int	rsv1:1;		/* Not used (always 0) */
		unsigned int	p:1;		/* present */
		unsigned int	rsv2:10;	/* Not used (always 0) */
		unsigned int	pfa:20;		/* page frame address */
	} c;
	UW	w;
} PDE;

/*
 * Page table entry
 *
 *	Combine present and valid to indicate the following states:
 *	 p = 0 va = 0	Page is absent
 *	 p = 0 va = 1	Page is suspended (see below)
 *	 p = 1 va = 0	Page is present and locked
 *	 p = 1 va = 1	Page is present
 *
 *	Combine copy-on-write and writable to indicate the following states:
 *	 cow = 1 w = 0	Before copy-on-write processing
 *	 cow = 1 w = 1	After copy-on-write processing
 *
 *	The states of pfa are as follows according to the situation:
 *	* When page is present (p = 1)
 *		pfa = physical page address
 *	* When page is absent (p = 0)
 *		* va = 1:
 *			pfa = physical page address
 *		* va = 0:
 *			pfa = 0			Invalid PTE
 *			pfa = 1 - PB_BASE-1	Disk map (map ID)
 *			pfa = PB_BASE - 0xfffff	Page file (block number)
 *
 *	pb = pfa - PB_BASE
 *		pb = 0	Page file not allocated
 *		pb > 0	Page file block number
 *
 *	(*)The mark indicates data not to be written to TLB.
 */
typedef union PageTablEntry {
	struct pte {
		unsigned int	g:1;		/* Shared space */
		unsigned int	p:1;		/* Page is valid. */
		unsigned int	d:1;		/* Dirty */
		unsigned int	c:1;		/* Cacheable */
		unsigned int	rsv1:1;		/* (*) Not used(always 0) */
		unsigned int	wb:1;		/* Write buffer (VR5500 only) */
		unsigned int	w:1;		/* (*) Writable */
		unsigned int	u:1;		/* (*) User accessible */
		unsigned int	a:1;		/* (*) Accessed */
		unsigned int	clr:1;		/* (*) Cleared at the time of page-in */
		unsigned int	cow:1;		/* (*) Copy-on-write */
		unsigned int	va:1;		/* (*) pfa is valid */
		unsigned int	pfa:20;		/* Physical page number */
	} c;
	UW	w;
} PTE;

#define	PB_BASE			( 0x00080000 )
#define	MAX_PFA			( 0x00100000U )

/* PDE,PTE bits */
#define	PT_Share		0x00000001U
#define	PT_Present		0x00000002U
#define	PT_Update		0x00000004U
#define	PT_Cachable		0x00000008U
#define	PT_WriteBuffer		0x00000020U	/* VR5500 only */
#define	PT_Writable		0x00000040U
#define	PT_User			0x00000080U
#define	PT_Accessed		0x00000100U
#define	PT_Clear		0x00000200U
#define	PT_CopyOnWrite		0x00000400U
#define	PT_Valid		0x00000800U
#define	PT_Address		0xfffff000U
#define	PT_PB_BASE		((UW)PB_BASE << 12U)

#define	isPresentP(pte)		( ((UW)(pte) & PT_Present) != 0U )
#define	isValidP(pte)		( ((UW)(pte) & PT_Valid) != 0U )
#define	isClearP(pte)		( ((UW)(pte) & PT_Clear) != 0U )
#define	isAccessedP(pte)	( ((UW)(pte) & PT_Accessed) != 0U )
#define	isUpdateP(pte)		( ((UW)(pte) & PT_Update) != 0U )
#define	isCopyOnWriteP(pte)	( ((UW)(pte) & PT_CopyOnWrite) != 0U )
#define	isWritableP(pte)	( ((UW)(pte) & PT_Writable) != 0U )
#define	isLockedP(pte)		( ((UW)(pte) & (PT_Present|PT_Valid)) \
					== (PT_Present) )
#define	CopyOnWriteP_done(pte)	( ((UW)(pte) & ((PT_CopyOnWrite)|(PT_Writable))) \
					== ((PT_CopyOnWrite)|(PT_Writable)) )

/*
 * Number of PTEs per page table
 */
#define	N_PTE	( (PAGESIZE) / sizeof(PTE) )

/*
 * Page directory setting value
 *	PDE_NONE	Invalid page directory entry
 *	PDE_NORM	Valid page directory entry
 */
#define	PDE_NONE	( 0 )
#define	PDE_NORM	( PT_Present )

/*
 * Page table setting value
 *	PTE_NONE	Invalid page directory entry
 *
 *			System memory initial entry
 *	PTE_SMEM_RO		Not writable
 *	PTE_SMEM_NC		Not cleared
 *	PTE_SMEM_CL		Cleared
 *	PTE_SMEM_CW		Copy-on-write (for change by disk map)
 *			User memory initial entry
 *	PTE_UMEM_RO		Not writable
 *	PTE_UMEM_NC		Not cleared
 *	PTE_UMEM_CL		Cleared
 *	PTE_UMEM_CW		Copy-on-write (for change by disk map)
 *
 *	PTE_DISKIO	Disk I/O entry
 */
#define	PTE_NONE	( 0 )
#define	PTE_SMEM_RO	( (PT_PB_BASE)|(PT_Cachable) )
#define	PTE_SMEM_NC	( (PTE_SMEM_RO)|(PT_Writable) )
#define	PTE_SMEM_CL	( (PTE_SMEM_NC)|(PT_Clear) )
#define	PTE_SMEM_CW	( PT_CopyOnWrite )
#define	PTE_UMEM_RO	( (PT_PB_BASE)|(PT_Cachable)|(PT_User) )
#define	PTE_UMEM_NC	( (PTE_UMEM_RO)|(PT_Writable) )
#define	PTE_UMEM_CL	( (PTE_UMEM_NC)|(PT_Clear) )
#define	PTE_UMEM_CW	( (PT_CopyOnWrite)|(PT_User) )
#define	PTE_DISKIO	( (PT_Present)|(PT_Writable)|(PT_Cachable)|(PT_Share) )

/*
 * Set cache off
 */
Inline UW PTE_CacheOff( UW pte )
{
	return pte & ~PT_Cachable;
}

/*
 * PTE setting value for disk map
 *	VR caching is performed with logical address. If multiple mapping (use several
 *	different logical addresses to map the same physical address) is performed, cache
 *	coherence is not maintained.
 *	Therefore, turn off the cache if pages are writable.
 */
Inline PTE PTE_DiskMap( ID mid, UW level )
{
	PTE	pte;
	pte.w = (level << 6) & (PT_Writable|PT_User);
	if ( pte.c.w == 0 ) {
		pte.w |= PT_Cachable;
	}
	pte.c.pfa = mid;
	return pte;
}

/*
 * PTE setting value for memory disk map
 */
Inline PTE PTE_MemDiskMap( UW level )
{
	PTE	pte;
	pte.w = ((level << 6) & (PT_Writable|PT_User))
			 | PT_Present;
	if ( pte.c.w == 0 ) {
		pte.w |= PT_Cachable;
	}
	return pte;
}

/*
 * Logical address mask
 */
#define	PDIR_MASK		0xffc00000U	/* Page directory */
#define	PTBL_MASK		0x003ff000U	/* Page table */
#define	POFS_MASK		0x00000fffU	/* Page offset */

#define	PDIR_NUM(laddr)		( (UW)(laddr) >> 22 )
#define	PTBL_NUM(laddr)		( ((UW)(laddr) & (PTBL_MASK)) >> 12 )
#define	POFS_NUM(laddr)		( (UW)(laddr) & (POFS_MASK) )

/*
 * Page frame address
 */
#define	PFAtoLADR(pfa)		( toLogicalAddress((UW)(pfa) << 12) )
#define	LADRtoPFA(laddr)	( (UW)toPhysicalAddress(laddr) >> 12 )

#define	PFAtoPADR(pfa)		( (VP)((UW)(pfa) << 12) )
#define	PADRtoPFA(paddr)	( (UW)(paddr) >> 12 )

/* ------------------------------------------------------------------------ */

/*
 * Page directory position (logical address)
 *	A unique space page directory is a table of unique spaces for the maximum number of
 *	processes + 1. At the start is a unique space for "lsid = 0" used in tasks that do
 *	not have unique spaces.
 *
 *	SATB and UATB are declared in the form of array so that they are not referred to by gp-relative.
 */
IMPORT	PDE	*_SATB[];	/* Shared space */
IMPORT	PDE	*_UATB[];	/* Unique space */

#define	SATB	( _SATB[0] )
#define	UATB	( _UATB[0] )

/*
 * Unique space: TRUE
 */
Inline BOOL isLocalSpace( VP laddr )
{
	return ( (UW)laddr < NUM_PDIR_ENTRIES * N_PTE * PAGESIZE );
}

/*
 * Area for loading system program: TRUE
 */
Inline BOOL isSysLoadSpace( VP laddr )
{
	return ( laddr >= (VP)SYSPRGSPACE_TOP && laddr < (VP)SYSPRGSPACE_END );
}

/*
 * Page table access handle
 */
typedef struct PageTableHandle {
	UW	lsid;		/* Intended logical space ID */
	VP	uatb;		/* Intended logical space UATB */
	VP	laddr;		/* Current logical address */
	PDE	*pde;		/* Current page directory */
	PTE	*pte;		/* Start of current page table */
	W	i;		/* Index in current page table */
} PTH;

/* ------------------------------------------------------------------------ */
/*
 *	TLB-related
 */

/*
 * Initialize TLB
 */
IMPORT void InitializeTLB( void );

/*
 * Purge the whole TLB
 */
IMPORT void PurgeAllTLB( void );

/*
 * Purge TLB that contains specified logical address.
 */
IMPORT void PurgePageTLB( VP laddr, UW lsid );

/*
 * Update TLB
 *	If there is an entry whose logical address matches the current TLB, update TLB;
 *	if not, register a new TLB.
 */
IMPORT void UpdateTLB( VP laddr, UW lsid, UW pte );

/* ------------------------------------------------------------------------ */
/*
 *	Cache-related
 */

/*
 * Cancel memory cache content (both instruction/data caches)
 *	Cancel (do not write back) a page (4KB) that contains laddr.
 *	Do not specify an invalid page (PTE.p=0).
 */
IMPORT void InvalidateCache( VP laddr, UW lsid );

/*
 * Flush memory cache (both instruction/data caches)
 *	Flush (write back) a page (4KB) that contains laddr and cancel it.
 *	Do not specify an invalid page (PTE.p=0).
 */
IMPORT void ExtFlushCache( VP laddr, UW lsid );

/*
 * Write back memory cache (data cache only).
 *	Write back (do not cancel) a page (4KB) that contains laddr.
 *	Do not specify an invalid page (PTE.p=0).
 */
IMPORT void FlushDCache( VP laddr, UW lsid );

/*
 * Flush memory cache (both instruction/data caches)
 *	Flush (write back) an area of size bytes starting from laddr and cancel it.
 *	Since the area is flushed on a page basis, it may include its preceding and succeeding areas.
 */
IMPORT void ExtFlushCacheArea( VP laddr, W size, UW lsid );

/*
 * Common cache control functions for segment management are shown below:
 */

/*
 * Synchronization between instruction and data caches (in any area)
 *	void SyncIDCacheArea( VP laddr, W size, UW lsid )
 *
 *	Synchronize contents of the instruction and data caches in an area of size bytes
 *	(starting from a logical address laddr) in logical space lsid. 
 *	It may include areas that are not paged in.
 */
#undef	SyncIDCacheArea
#define	SyncIDCacheArea(laddr, size, lsid)  ExtFlushCacheArea(laddr, size, lsid)

/*
 * Write back data cache (one page)
 *	void WriteBackDCachePage( VP laddr, UW lsid )
 *
 *	Cancel data cache content of one page that includes a logical
 *	address laddr in lsid logical space by writing the content
 *	to memory for synchronization.
 *	It is necessary that the page including laddr has been paged in.
 */
#undef	WriteBackDCachePage
#define	WriteBackDCachePage(laddr, lsid)	ExtFlushCache(laddr, lsid)

/*
 * Cancel cache (one page)
 *	void InvalidateCachePage( VP laddr, UW lsid )
 *
 *	Cancel cache content of one page that includes a logical
 *	address laddr in lsid logical space.
 *	Data cache is not written back.
 *	It is necessary that the page including laddr has been paged in.
 */
#undef	InvalidateCachePage
#define	InvalidateCachePage(laddr, lsid)	InvalidateCache(laddr, lsid)

/* ------------------------------------------------------------------------ */

#include <sys/sysinfo.h>

/*
 * TLB-related exception codes
 */
#define	EXC_TLBMISS	EIT_TLBMISS	/* TLB inconsistency */
#define	EXC_XTLBMISS	EIT_XTLBMISS	/* XTLB inconsistency */
#define	EXC_TLBMOD	EIT_EXC(1)	/* TLB changed */
#define	EXC_TLBINV_L	EIT_EXC(2)	/* TLB invalid (load) */
#define	EXC_TLBINV_S	EIT_EXC(3)	/* TLB invalid (store) */

/*
 * Set low-level handler
 */
Inline void define_inthdr( INT intvec, FP inthdr )
{
	SCArea->intvec[intvec] = inthdr;

	/* Write back cache */
	Asm("cache (6 << 2)|1, (%0)":: "r"(&SCArea->intvec[intvec]));
}

#endif