cnt1.srr

程序补充说明：对于时序逻辑

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Wed Mar 08 20:34:47 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\prj\Example-4-1\source\cnt1.v"
Verilog syntax check successful!
Selecting top level module cnt1
@N:"C:\prj\Example-4-1\source\cnt1.v":1:7:1:10|Synthesizing module cnt1

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Mar 08 20:34:48 2006

###########################################################[
Version 8.1
Synplicity CPLD Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
@N:"c:\prj\example-4-1\source\cnt1.v":7:2:7:7|Found counter in view:work.cnt1(verilog) inst cnt_out[3:0]
---------------------------------------
Resource Usage Report

Simple gate primitives:
DFF             4 uses
IBUF            1 use
OBUF            4 uses
XOR2            3 uses
AND2            2 uses
INV             1 use


@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################]