📄 crc73.mdl
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Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType TriggerPort
TriggerType "rising"
StatesWhenEnabling "inherit"
ShowOutputPort off
OutputDataType "auto"
SampleTimeType "triggered"
SampleTime "1"
ZeroCross on
}
Block {
BlockType UnitDelay
X0 "0"
SampleTime "1"
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "crc73"
Location [2, 78, 1014, 709]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Binary Vector\nNoise Generator"
Ports [0, 1]
Position [820, 113, 900, 157]
SourceBlock "commnoisgen2/Binary Error\nPattern Generator"
SourceType "Binary Error Pattern Generator"
n "5"
prob "0.5"
seed "12345"
Ts "1"
frameBased off
blksPerFrame "1"
orient off
}
Block {
BlockType Reference
Name "Clock"
Ports [0, 1]
Position [75, 541, 115, 569]
SourceBlock "simulink_extras/Flip Flops/Clock"
SourceType "Digital clock"
ShowPortLabels on
MaskParam1 "2"
}
Block {
BlockType Reference
Name "D Flip-Flop"
Ports [3, 2]
Position [215, 462, 260, 538]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
}
Block {
BlockType Reference
Name "D Flip-Flop1"
Ports [3, 2]
Position [280, 467, 325, 543]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
}
Block {
BlockType Reference
Name "D Flip-Flop10"
Ports [3, 2]
Position [455, 137, 500, 213]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
}
Block {
BlockType Reference
Name "D Flip-Flop11"
Ports [3, 2]
Position [575, 142, 620, 218]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
}
Block {
BlockType Reference
Name "D Flip-Flop2"
Ports [3, 2]
Position [355, 462, 400, 538]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
}
Block {
BlockType Reference
Name "D Flip-Flop3"
Ports [3, 2]
Position [425, 457, 470, 533]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
}
Block {
BlockType Reference
Name "D Flip-Flop8"
Ports [3, 2]
Position [145, 142, 190, 218]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
}
Block {
BlockType Reference
Name "D Flip-Flop9"
Ports [3, 2]
Position [300, 142, 345, 218]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [235, 72, 265, 103]
Operator "NOR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical\nOperator1"
Ports [2, 1]
Position [390, 72, 420, 103]
Operator "NOR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical\nOperator2"
Ports [2, 1]
Position [750, 192, 780, 223]
Operator "NOR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical\nOperator3"
Ports [4, 1]
Position [565, 307, 595, 338]
Operator "NOR"
Inputs "4"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical\nOperator4"
Ports [2, 1]
Position [855, 417, 885, 448]
Operator "NOR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical\nOperator5"
Ports [2, 1]
Position [750, 52, 780, 83]
Operator "NOR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType MATLABFcn
Name "MATLAB Fcn"
Position [955, 120, 1015, 150]
MATLABFcn "crcgen1"
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [960, 414, 990, 446]
Location [188, 390, 512, 629]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
DataFormat "StructureWithTime"
}
Line {
SrcBlock "D Flip-Flop1"
SrcPort 1
Points [5, 0; 0, -10]
DstBlock "D Flip-Flop2"
DstPort 1
}
Line {
SrcBlock "Clock"
SrcPort 1
Points [35, 0]
Branch {
Points [0, 55; 110, 0]
Branch {
Points [0, -85]
Branch {
DstBlock "D Flip-Flop1"
DstPort 2
}
Branch {
DstBlock "D Flip-Flop1"
DstPort 3
}
}
Branch {
Points [75, 0]
Branch {
Points [0, -85]
Branch {
DstBlock "D Flip-Flop2"
DstPort 2
}
Branch {
DstBlock "D Flip-Flop2"
DstPort 3
}
}
Branch {
Points [70, 0; 0, -95]
Branch {
DstBlock "D Flip-Flop3"
DstPort 2
}
Branch {
DstBlock "D Flip-Flop3"
DstPort 3
}
}
}
}
Branch {
Points [0, -30]
Branch {
DstBlock "D Flip-Flop"
DstPort 3
}
Branch {
Points [0, -25]
Branch {
DstBlock "D Flip-Flop"
DstPort 2
}
Branch {
Points [-40, 0; 0, -290]
Branch {
Points [0, -5]
DstBlock "D Flip-Flop8"
DstPort 3
}
Branch {
Points [0, -30]
DstBlock "D Flip-Flop8"
DstPort 2
}
}
Branch {
Points [30, 0; 0, -85]
Branch {
Points [-10, 0; 0, -235; 65, 0]
Branch {
DstBlock "D Flip-Flop9"
DstPort 2
}
Branch {
Points [0, 25]
DstBlock "D Flip-Flop9"
DstPort 3
}
}
Branch {
Points [0, -40; 255, 0; 0, -70]
Branch {
Points [0, -110]
Branch {
DstBlock "D Flip-Flop10"
DstPort 2
}
Branch {
DstBlock "D Flip-Flop10"
DstPort 3
}
}
Branch {
Points [80, 0; 0, -100]
Branch {
Points [0, -25]
DstBlock "D Flip-Flop11"
DstPort 2
}
Branch {
DstBlock "D Flip-Flop11"
DstPort 3
}
}
}
}
}
}
}
Line {
SrcBlock "D Flip-Flop"
SrcPort 1
DstBlock "D Flip-Flop1"
DstPort 1
}
Line {
SrcBlock "D Flip-Flop2"
SrcPort 1
Points [0, -10]
DstBlock "D Flip-Flop3"
DstPort 1
}
Line {
SrcBlock "D Flip-Flop8"
SrcPort 1
Points [20, 0; 0, -65]
DstBlock "Logical\nOperator"
DstPort 2
}
Line {
SrcBlock "D Flip-Flop9"
SrcPort 1
Points [10, 0; 0, -65]
DstBlock "Logical\nOperator1"
DstPort 2
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
Points [5, 0; 0, 65]
DstBlock "D Flip-Flop9"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator1"
SrcPort 1
Points [5, 0; 0, 60]
DstBlock "D Flip-Flop10"
DstPort 1
}
Line {
SrcBlock "D Flip-Flop10"
SrcPort 1
DstBlock "D Flip-Flop11"
DstPort 1
}
Line {
SrcBlock "D Flip-Flop11"
SrcPort 1
Points [30, 0]
Branch {
Points [25, 0; 0, 40]
DstBlock "Logical\nOperator2"
DstPort 1
}
Branch {
Points [0, 140; -105, 0]
DstBlock "Logical\nOperator3"
DstPort 1
}
}
Line {
SrcBlock "Logical\nOperator2"
SrcPort 1
Points [0, -95; -50, 0]
DstBlock "Logical\nOperator5"
DstPort 2
}
Line {
SrcBlock "Logical\nOperator5"
SrcPort 1
Points "[0, -25; -175, 0; 0, 30; -180, 0; 0, -15; -55, "
"0; 0, 5]"
Branch {
DstBlock "Logical\nOperator1"
DstPort 1
}
Branch {
Points [-155, 0; 0, 5]
Branch {
DstBlock "Logical\nOperator"
DstPort 1
}
Branch {
Points [-90, 0]
DstBlock "D Flip-Flop8"
DstPort 1
}
}
}
Line {
SrcBlock "D Flip-Flop8"
SrcPort 2
Points [35, 0; 0, 130]
DstBlock "Logical\nOperator3"
DstPort 4
}
Line {
SrcBlock "D Flip-Flop9"
SrcPort 2
Points [0, 125]
DstBlock "Logical\nOperator3"
DstPort 3
}
Line {
SrcBlock "D Flip-Flop10"
SrcPort 2
Points [45, 0]
DstBlock "Logical\nOperator3"
DstPort 2
}
Line {
SrcBlock "Logical\nOperator3"
SrcPort 1
Points [70, 0]
Branch {
Points [30, 0; 0, 100]
DstBlock "Logical\nOperator4"
DstPort 1
}
Branch {
Points [0, -110]
DstBlock "Logical\nOperator2"
DstPort 2
}
}
Line {
SrcBlock "Logical\nOperator4"
SrcPort 1
Points [55, 0]
DstBlock "Scope"
DstPort 1
}
Line {
SrcBlock "D Flip-Flop3"
SrcPort 1
Points [180, 0; 0, -35]
DstBlock "Logical\nOperator4"
DstPort 2
}
Line {
SrcBlock "Binary Vector\nNoise Generator"
SrcPort 1
DstBlock "MATLAB Fcn"
DstPort 1
}
Line {
SrcBlock "MATLAB Fcn"
SrcPort 1
Points [5, 0; 0, -115; -115, 0]
Branch {
Points [-175, 0]
DstBlock "Logical\nOperator5"
DstPort 1
}
Branch {
Points [-710, 0]
DstBlock "D Flip-Flop"
DstPort 1
}
}
}
}
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