p89c58_plus.h

一个基于SJA1000的CAN总线通讯程序

#ifndef P89C58_PLUS_H
#define P89C58_PLUS_H
/*--------------------------------------------------------------------------
Header file for 8xC31/51, 80C51Fx, 80C51Rx+
SFR's AUXR and AUXR1 added for 80C51Rx+ derivatives
--------------------------------------------------------------------------*/

/*  BYTE Registers  */
sfr P0   = 0x80;
sfr P1   = 0x90;
sfr P2   = 0xA0;
sfr P3   = 0xB0;
sfr PSW  = 0xD0;
sfr ACC  = 0xE0;
sfr B    = 0xF0;
sfr SP   = 0x81;
sfr DPL  = 0x82;
sfr DPH  = 0x83;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0  = 0x8A;
sfr TL1  = 0x8B;
sfr TH0  = 0x8C;
sfr TH1  = 0x8D;
sfr IE   = 0xA8;
sfr IP   = 0xB8;
sfr SCON = 0x98;
sfr SBUF = 0x99;

/*  80C51Fx/Rx Extensions  */
sfr AUXR   = 0x8E;
sfr AUXR1  = 0xA2;
sfr SADDR  = 0xA9;
sfr IPH    = 0xB7;
sfr SADEN  = 0xB9;
sfr T2CON  = 0xC8;
sfr T2MOD  = 0xC9;
sfr RCAP2L = 0xCA;
sfr RCAP2H = 0xCB;
sfr TL2    = 0xCC;
sfr TH2    = 0xCD;

/* STC Extensions */
sfr P4        = 0xE8;
sfr XICON     = 0xC0;
sfr WDT_CONTR = 0xE1;
sfr ISP_DATA  = 0xE2;
sfr ISP_ADDRH = 0xE3;
sfr ISP_ADDRL = 0xE4;
sfr ISP_CMD   = 0xE5;
sfr ISP_TRIG  = 0xE6;
sfr ISP_CONTR = 0xE7;

/*  BIT Registers  */
/*  PSW   */
sbit CY   = PSW^7;
sbit AC   = PSW^6;
sbit F0   = PSW^5;
sbit RS1  = PSW^4;
sbit RS0  = PSW^3;
sbit OV   = PSW^2;
sbit P    = PSW^0;

/*  TCON  */
sbit TF1  = TCON^7;
sbit TR1  = TCON^6;
sbit TF0  = TCON^5;
sbit TR0  = TCON^4;
sbit IE1  = TCON^3;
sbit IT1  = TCON^2;
sbit IE0  = TCON^1;
sbit IT0  = TCON^0;

/*  IE   */
sbit EA   = IE^7;

sbit ET2  = IE^5;
sbit ES   = IE^4;
sbit ET1  = IE^3;
sbit EX1  = IE^2;
sbit ET0  = IE^1;
sbit EX0  = IE^0;

/*  IP   */
sbit PT2  = IP^5;
sbit PS   = IP^4;
sbit PT1  = IP^3;
sbit PX1  = IP^2;
sbit PT0  = IP^1;
sbit PX0  = IP^0;

/*  IPH   
sbit PX3H = IPH^7;
sbit PX2H = IPH^6;
sbit PT2H = IPH^5;
sbit PSH  = IPH^4;
sbit PT1H = IPH^3;
sbit PX1H = IPH^2;
sbit PT0H = IPH^1;
sbit PX0H = IPH^0;*/

/*  XICON   */
sbit PX3  = XICON^7;
sbit EX3  = XICON^6;
sbit IE3  = XICON^5;
sbit IT3  = XICON^4;
sbit PX2  = XICON^3;
sbit EX2  = XICON^2;
sbit IE2  = XICON^1;
sbit IT2  = XICON^0;

/*  P3  */
sbit RD   = P3^7;
sbit WR   = P3^6;
sbit T1   = P3^5;
sbit T0   = P3^4;
sbit INT1 = P3^3;
sbit INT0 = P3^2;
sbit TXD  = P3^1;
sbit RXD  = P3^0;

/*  P4  */
sbit INT2 = P4^3;
sbit INT3 = P4^2;

/*  SCON  */
sbit SM0  = SCON^7; // alternatively "FE"
sbit FE   = SCON^7;
sbit SM1  = SCON^6;
sbit SM2  = SCON^5;
sbit REN  = SCON^4;
sbit TB8  = SCON^3;
sbit RB8  = SCON^2;
sbit TI   = SCON^1;
sbit RI   = SCON^0;

/*   P1    */
sbit T2EX = P1^1;
sbit T2   = P1^0;

/*  T2CON  */
sbit TF2   = T2CON^7;
sbit EXF2  = T2CON^6;
sbit RCLK  = T2CON^5;
sbit TCLK  = T2CON^4;
sbit EXEN2 = T2CON^3;
sbit TR2   = T2CON^2;
sbit C     = T2CON^1;
sbit _T2   = T2CON^1;
sbit CP    = T2CON^0;
sbit _RL2  = T2CON^0;

/*  AUXR  
sbit AUXRAM = AUXR^1; //0, enable AUX_RAM; 1, disable AUX_RAM
sbit ALEOFF = AUXR^0; //0, enable ALE OUT; 1, disable ALE OUT */

/*  AUXR1  
sbit GF2   = AUXR1^3; //General purpose user-defined flag
sbit DPS   = AUXR1^0; //0, select DPTR; 1, select DPTR1 */

/*  WDT_CONTR  
sbit EN_WDT   = WDT_CONTR^5;
sbit CLR_WDT  = WDT_CONTR^4;
sbit IDLE_WDT = WDT_CONTR^3;
sbit PS2      = WDT_CONTR^2;
sbit PS1      = WDT_CONTR^1;
sbit PS0      = WDT_CONTR^0;*/

#define uchar 	unsigned char
#define uint    unsigned int
#define ulong   unsigned long

sbit    WDI = P1^2;
#define kickdog WDI = !WDI;

#endif