sja1000.h

一个基于SJA1000的CAN总线通讯程序

#define SJA_REG			0x8000

//...Control register section...
#define SJA_REG_CR	XBYTE[SJA_REG + 0x00] // Control Register
#define SJA_REG_CMD	XBYTE[SJA_REG + 0x01] // Command Register
#define SJA_REG_SR	XBYTE[SJA_REG + 0x02] // Status register
#define SJA_REG_IR	XBYTE[SJA_REG + 0x03] // Interrupt register
#define SJA_REG_ACR	XBYTE[SJA_REG + 0x04] // Acceptance code register
#define SJA_REG_AMR	XBYTE[SJA_REG + 0x05] // Acceptance code register
#define SJA_REG_BTR0	XBYTE[SJA_REG + 0x06] // Bus timing 0
#define SJA_REG_BTR1	XBYTE[SJA_REG + 0x07] // Bus timing 1
#define SJA_REG_OCR	XBYTE[SJA_REG + 0x08] // Output control
#define SJA_REG_TEST	XBYTE[SJA_REG + 0x09] // Test register

//...Transmit buffer section...
#define SJA_REG_TxBuf0	XBYTE[SJA_REG + 0x0A] // Transmit buffer register 0
#define SJA_REG_TxBuf1	XBYTE[SJA_REG + 0x0B] // Transmit buffer register 1
#define SJA_REG_TxBuf2	XBYTE[SJA_REG + 0x0C] // Transmit buffer register 2
#define SJA_REG_TxBuf3	XBYTE[SJA_REG + 0x0D] // Transmit buffer register 3
#define SJA_REG_TxBuf4	XBYTE[SJA_REG + 0x0E] // Transmit buffer register 4
#define SJA_REG_TxBuf5	XBYTE[SJA_REG + 0x0F] // Transmit buffer register 5
#define SJA_REG_TxBuf6	XBYTE[SJA_REG + 0x10] // Transmit buffer register 6
#define SJA_REG_TxBuf7	XBYTE[SJA_REG + 0x11] // Transmit buffer register 7
#define SJA_REG_TxBuf8	XBYTE[SJA_REG + 0x12] // Transmit buffer register 8
#define SJA_REG_TxBuf9	XBYTE[SJA_REG + 0x13] // Transmit buffer register 9

//...Receive buffer section...
#define SJA_REG_RxBuf0	XBYTE[SJA_REG + 0x14] // Receive buffer register 0
#define SJA_REG_RxBuf1	XBYTE[SJA_REG + 0x15] // Receive buffer register 1
#define SJA_REG_RxBuf2	XBYTE[SJA_REG + 0x16] // Receive buffer register 2
#define SJA_REG_RxBuf3	XBYTE[SJA_REG + 0x17] // Receive buffer register 3
#define SJA_REG_RxBuf4	XBYTE[SJA_REG + 0x18] // Receive buffer register 4
#define SJA_REG_RxBuf5	XBYTE[SJA_REG + 0x19] // Receive buffer register 5
#define SJA_REG_RxBuf6	XBYTE[SJA_REG + 0x1A] // Receive buffer register 6
#define SJA_REG_RxBuf7	XBYTE[SJA_REG + 0x1B] // Receive buffer register 7
#define SJA_REG_RxBuf8	XBYTE[SJA_REG + 0x1C] // Receive buffer register 8
#define SJA_REG_RxBuf9	XBYTE[SJA_REG + 0x1D] // Receive buffer register 9

#define SJA_REG_CDR	XBYTE[SJA_REG + 0x1F] // Clock divider register