📄 exm08051_1.mdl
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Model {
Name "exm08051_1"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip on
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Mon Dec 13 13:33:20 1999"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "wangjun"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Sun Nov 17 16:31:06 2002"
ModelVersionFormat "1.%<AutoIncrement:4>"
ConfigurationManager "none"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "oneshot"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect off
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints off
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType off
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType CombinatorialLogic
TruthTable "[0 0;0 1;0 1;1 0;0 1;1 0;1 0;1 1]"
}
Block {
BlockType Constant
Value "1"
VectorParams1D on
ShowAdditionalParam off
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
}
Block {
BlockType Demux
Outputs "4"
DisplayOption "none"
BusSelectionMode off
}
Block {
BlockType Display
Format "short"
Decimation "10"
Floating off
SampleTime "-1"
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
ShowAdditionalParam off
AllPortsSameDT on
OutDataTypeMode "Logical (see Advanced Sim. Parameters)"
LogicDataType "uint(8)"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "exm08051_1"
Location [22, 91, 502, 284]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Display
Name "C-D1"
Ports [1]
Position [315, 35, 405, 65]
Orientation "left"
Decimation "1"
}
Block {
BlockType Display
Name "C-D2"
Ports [1]
Position [315, 85, 405, 115]
Orientation "left"
Decimation "1"
}
Block {
BlockType CombinatorialLogic
Name "C-Logic"
Position [160, 135, 190, 165]
TruthTable "[0 0;0 1;0 1;1 1]"
Port {
PortNumber 1
Name "c"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Display
Name "D1"
Ports [1]
Position [215, 35, 305, 65]
Decimation "1"
}
Block {
BlockType Display
Name "D2"
Ports [1]
Position [215, 85, 305, 115]
Decimation "1"
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 2]
Position [440, 56, 445, 94]
Orientation "left"
BackgroundColor "black"
ShowName off
Outputs "2"
Port {
PortNumber 1
Name "c(1)"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
Port {
PortNumber 2
Name "c(2)"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Logic
Name "Logic 1"
Ports [2, 1]
Position [160, 32, 190, 63]
}
Block {
BlockType Logic
Name "Logic 2"
Ports [2, 1]
Position [160, 82, 190, 113]
Operator "OR"
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1]
Position [125, 131, 130, 169]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Constant
Name "a"
Position [50, 30, 80, 50]
}
Block {
BlockType Constant
Name "b"
Position [50, 150, 80, 170]
NamePlacement "alternate"
Value "0"
}
Line {
SrcBlock "Logic 2"
SrcPort 1
DstBlock "D2"
DstPort 1
}
Line {
SrcBlock "a"
SrcPort 1
Points [20, 0]
Branch {
DstBlock "Logic 1"
DstPort 1
}
Branch {
Points [0, 50]
Branch {
Points [0, 50]
DstBlock "Mux"
DstPort 1
}
Branch {
DstBlock "Logic 2"
DstPort 1
}
}
}
Line {
SrcBlock "Logic 1"
SrcPort 1
DstBlock "D1"
DstPort 1
}
Line {
SrcBlock "b"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Mux"
DstPort 2
}
Branch {
Points [0, -55]
Branch {
Points [0, -50]
DstBlock "Logic 1"
DstPort 2
}
Branch {
DstBlock "Logic 2"
DstPort 2
}
}
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "C-Logic"
DstPort 1
}
Line {
Name "c(1)"
Labels [2, 1]
SrcBlock "Demux"
SrcPort 1
Points [-15, 0]
DstBlock "C-D1"
DstPort 1
}
Line {
Name "c(2)"
Labels [-1, 0]
SrcBlock "Demux"
SrcPort 2
Points [-15, 0]
DstBlock "C-D2"
DstPort 1
}
Line {
Name "c"
Labels [0, 0]
SrcBlock "C-Logic"
SrcPort 1
Points [265, 0]
DstBlock "Demux"
DstPort 1
}
Annotation {
Name "Mux"
Position [125, 125]
}
Annotation {
Name "Demux"
Position [437, 42]
}
}
}
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