datatype.h

linux下nand flash驱动

#define D12_EP1_OUT						0x02
#define D12_EP1_IN						0x03
#define D12_EP2_OUT						0x04
#define D12_EP2_IN						0x05
// Distinguish Command/Data
#define D12_COMMAND						0x55
#define D12_DATA						0xaa

// PDIUSBD12 Register Bits Descriptions in Chip
// Set Mode Byte 1
#define D12_NO_LAZY_CLOCK		0x02
#define D12_CLOCK_RUNNING		0x04
#define D12_INTERRUPT_MODE		0x08
#define D12_SOFT_CONNECT		0x10
#define D12_EP_NON_ISO			0x00
#define D12_EP_ISO_OUT			0x40
#define D12_EP_ISO_IN			0x80
#define D12_EP_ISO_IO			0xC0
// Set Mode Byte 2
#define D12_CLOCK_48M			0x00
#define D12_CLOCK_24M			0x01
#define D12_CLOCK_16M			0x02
#define D12_CLOCK_12M			0x03
#define D12_CLOCK_8M			0x05
#define D12_CLOCK_6M			0x07
#define D12_CLOCK_4M			0x0b
#define D12_CLOCK_3M			0x0f
#define D12_SET_TO_ONE			0x40
#define D12_SOF_ONLY			0x80
// Set DMA
#define D12_DMA_SINGLE			0x00
#define D12_DMA_BURST_4			0x01
#define D12_DMA_BURST_8			0x02
#define D12_DMA_BURST_16		0x03
#define D12_DMA_ENABLE			0x04
#define D12_DMA_INTOKEN			0x08
#define D12_DMA_AUTOLOAD		0x10
#define D12_DMA_NORMAL_PLUS_SOF	0x20
#define D12_DMA_EP4_INT_ENABLE	0x40
#define D12_DMA_EP5_INT_ENABLE	0x80
// Interrupt Register
#define D12_INT_EP0_OUT			0x01
#define D12_INT_EP0_IN			0x02
#define D12_INT_EP1_OUT			0x04
#define D12_INT_EP1_IN			0x08
#define D12_INT_EP2_OUT			0x10
#define D12_INT_EP2_IN			0x20
#define D12_INT_BUS_RESET		0x40
#define D12_INT_SUSPEND_CHANGE	0x80
#define D12_INT_DMA_EOT			0x0100
// Last Transaction Status Register
#define D12_TRANSMIT_SUCCESS	0x01
#define D12_ERROR_MASK			0x1e
#define D12_SETUPPACKET			0x20
#define D12_DATA01				0x40
#define D12_PREVIOUS_STATUS		0x80
// Error Code
#define D12_ERR_NON				0x00
#define D12_ERR_PID_ENCODE		0x01
#define D12_ERR_PID_UNKNOWN		0x02
#define D12_ERR_UNEXPECT_PACKET	0x03
#define D12_ERR_TOKEN_CRC		0x04
#define D12_ERR_DATA_CRC		0x05
#define D12_ERR_TIME_OUT		0x06
#define D12_ERR_NEVER_HAPPEN	0x07
#define D12_ERR_UNEXPECT_EOP	0x08
#define D12_ERR_NAK				0x09
#define D12_ERR_SENT_STALL		0x0a
#define D12_ERR_OVERFLOW		0x0b
#define D12_ERR_RESERVED1		0x0c
#define D12_ERR_BIT_STUFF		0x0d
#define D12_ERR_RESERVED2		0x0e
#define D12_ERR_WRONG_DATA_PID	0x0f
#define D12_BUFFER0FULL			0x20
#define D12_BUFFER1FULL			0x40
#define D12_FULLEMPTY			0x01
#define D12_STALL				0x02
// Special Const for PDIUSBD12
#define D12_MAX_ENDPOINTS		0x03
// EP0
#define D12_EP0_PACKET_SIZE		0x10
#define D12_EP0_TX_FIFO_SIZE	0x10
#define D12_EP0_RX_FIFO_SIZE	0x10
// EP1
#define D12_EP1_PACKET_SIZE		0x10
#define D12_EP1_TX_FIFO_SIZE	0x10
#define D12_EP1_RX_FIFO_SIZE	0x10
// EP2
#define D12_EP2_PACKET_SIZE		0x40
#define D12_EP2_TX_FIFO_SIZE	0x40
#define D12_EP2_RX_FIFO_SIZE	0x40
// Redefinition Port and Mask for Controlling PDIUSBD12 Chip
// Mask
// Chip Select Control
#define USB_CS			0x01			//Modified by Mike Chan
// Read/Write Control
#define USB_RW			0x60
#define USB_READ		0x20
#define USB_WRITE		0x40
// Other Control
#define USB_SUSPEND		0x04
#define USB_OC			0x10
#define USB_A0			0x10			//Modified by Mike Chan
// Control Interrupt

#define BASE_ADDR		0x3000020
//0x10E00000
// ATA register
#define DATA_REG				BASE_ADDR			//Data Register
#define ERROR_REG				BASE_ADDR+2	//Error register
#define SECTOR_COUNT_REG		BASE_ADDR+4	//Interrupt Reason Register
#define SECTOR_NUMBER_REG		BASE_ADDR+6	//Reserved
#define CYLINDER_LOW_REG		BASE_ADDR+8	//Byte Count Low
#define CYLINDER_HIGH_REG		BASE_ADDR+10	//Byte Count High Register
#define DRIVE_HEAD_REG			BASE_ADDR+12	//Drive Select Register
#define STATUS_REG				BASE_ADDR+14	//Status or command Register
#define FEATURE_REG         	ERROR_REG
#define COMMAND_REG         	STATUS_REG

// ATAPI specific register
#define INTERRUPT_REASON_REG    SECTOR_COUNT_REG
#define BYTE_COUNT_LOW_REG      CYLINDER_LOW_REG
#define BYTE_COUNT_HIGH_REG     CYLINDER_HIGH_REG
// ATA status
#define ATA_STATUS_BSY      0x80
#define ATA_STATUS_DRDY     0x40
#define ATA_STATUS_DRQ      0x08
#define ATA_STATUS_ERR      0x01
#define ATA_Packet_CD       0x01
//Error Code
#define	NO_ERROR			0x00
#define DRIVE_NOT_REDAY		0x04
#define	DRIVE_CHANGED		0x60
//The parameter of ATAPI command
#define	ID_RD				0			//Read
#define	ID_WR				1			//Write
#define	ID_OTHERS			2			//Other Command
#define	ID_SET				3			//Set parameter


#define Read_ATA_Reg(reg) (*((volatile unsigned char*) reg))
#define Write_ATA_Reg(reg, c)	(*((volatile unsigned char *) reg) = (unsigned char)c)
#define Read_ATA_Data_Reg()	(*((volatile unsigned short*) DATA_REG))
#define Write_ATA_Data_Reg(n) (*((volatile unsigned short*) DATA_REG) = (unsigned short)n)

/*define end*/




/************************************************************/
extern void  TPBulk_ClassRequestHandler( void );
extern void  TPBulk_CBWHandler(void);
extern void  TPBulk_CSWHandler(void);
extern void  TPBulk_SingleTransmitEP0(UCHAR *buf, UCHAR len);
/************************************************************/
#define  LBLOCKSZ			0x200	//rbc
extern UCHAR IOZip_AtapiHandle(void);
/************************************************************/
extern void get_status(void);		//Protocol
extern void clear_feature(void);
extern void set_feature(void);
extern void set_address(void);
extern void get_descriptor(void);
extern void get_configuration(void);
extern void set_configuration(void);
extern void get_interface(void);
extern void set_interface(void);
extern void reserved(void);
/************************************************************/
extern void  outportb(UCHAR cmdordata, UCHAR cmddata);
extern UCHAR inportb(UCHAR cmdordata);

extern void  D12_SetAddressEnable(UCHAR bAddress, UCHAR bEnable);
extern void  D12_SetEndpointEnable(UCHAR bEnable);
extern void  D12_SetMode(UCHAR bConfig, UCHAR bClkDiv);
extern void  D12_SetDMA(UCHAR bMode);
extern UWORD D12_ReadInterruptRegister(void);
extern UCHAR D12_SelectEndpoint(UCHAR bEndp);
extern UCHAR D12_ReadLastTransactionStatus(UCHAR bEndp);
extern UCHAR D12_ReadEndpointStatus(UCHAR bEndp);
extern void  D12_SetEndpointStatus(UCHAR bEndp, UCHAR bStalled);
extern void  D12_SendResume(void);
extern UWORD D12_ReadCurrentFrameNumber(void);

extern UCHAR D12_ReadEndpoint(UCHAR endp, UCHAR *buf, UCHAR len);
extern UCHAR D12_WriteEndpoint(UCHAR endp, UCHAR *buf, UCHAR len);
extern void  D12_AcknowledgeEndpoint(UCHAR endp);
extern UCHAR D12_ReadMainEndpoint(UCHAR * buf);

// Addition
extern void  stall_ep0(void);
extern void  Stall_EP2(void);
extern void  single_transmit(UCHAR *buf, UCHAR len);
extern void  code_transmit(UCHAR *pRomData, UWORD welen);
extern void  init_unconfig(void);
extern void  init_config(void);
extern void  usb_isr(int irq, void* dev_id, struct pt_regs* regs);
/************************************************************/
extern void  Usb_Main(void);
/************************************************************/
extern void  usb_initialize(void);
/************************************************************/
//extern unsigned short Exec_ATAPI_Command();
extern unsigned short Exec_ATAPI_Command1();
/************************************************************/

//extern unsigned char Command[12];
extern unsigned char Allbuffer[0x10000L];
extern unsigned long Buffer_Length;
extern unsigned char* Buffer_Pointer;
extern unsigned char Id;
extern CONTROL_XFER ControlData;
extern EPPFLAGS		bEPPflags;
extern D12FLAGS		bD12flags;
//extern CBW			TPBulk_CommandBlock;
//extern CSW			TPBulk_CommandStatus;
extern UCHAR CBWBuf[31];
extern UCHAR CSWBuf[13];
extern int connectflag;
#define TPBulk_CommandBlock_dCBW_Signature 			(*((ULONG *)&CBWBuf[0]))
#define TPBulk_CommandBlock_dCBW_Tag				(*((ULONG *)&CBWBuf[4]))
#define TPBulk_CommandBlock_dCBW_DataXferLen		(*((ULONG *)&CBWBuf[8]))
#define TPBulk_CommandBlock_bCBW_Flag				CBWBuf[12]
#define TPBulk_CommandBlock_bCBW_LUN				CBWBuf[13]
#define TPBulk_CommandBlock_bCBW_CDBLen				CBWBuf[14]
#define TPBulk_CommandBlock_bAtapi_CommandPackage0	CBWBuf[15]
#define TPBulk_CommandBlock_bAtapi_CommandPackage1	CBWBuf[16]
#define TPBulk_CommandBlock_bAtapi_CommandPackage2	CBWBuf[17]
#define TPBulk_CommandBlock_bAtapi_CommandPackage3	CBWBuf[18]
#define TPBulk_CommandBlock_bAtapi_CommandPackage4	CBWBuf[19]
#define TPBulk_CommandBlock_bAtapi_CommandPackage5	CBWBuf[20]
#define TPBulk_CommandBlock_bAtapi_CommandPackage6	CBWBuf[21]
#define TPBulk_CommandBlock_bAtapi_CommandPackage7	CBWBuf[22]
#define TPBulk_CommandBlock_bAtapi_CommandPackage8	CBWBuf[23]
#define TPBulk_CommandBlock_bAtapi_CommandPackage9	CBWBuf[24]
#define TPBulk_CommandBlock_bAtapi_CommandPackage10	CBWBuf[25]
#define TPBulk_CommandBlock_bAtapi_CommandPackage11	CBWBuf[26]
#define TPBulk_CommandBlock_bAtapi_CommandPackage12	CBWBuf[27]
#define TPBulk_CommandBlock_bAtapi_CommandPackage13	CBWBuf[28]
#define TPBulk_CommandBlock_bAtapi_CommandPackage14	CBWBuf[29]
#define TPBulk_CommandBlock_bAtapi_CommandPackage15	CBWBuf[30]

#define TPBulk_CommandStatus_dCSW_Signature 	(*((ULONG *)&CSWBuf[0]))
#define TPBulk_CommandStatus_dCSW_Tag			(*((ULONG *)&CSWBuf[4]))
#define TPBulk_CommandStatus_dCSW_DataResidue	(*((ULONG *)&CSWBuf[8]))
#define TPBulk_CommandStatus_bCSW_Status		CSWBuf[12]

//#define cli()	IMR |= 0x00040000
//#define sti()	IMR &= ~0x00040000;

//#define printk 	printf
/*#define BUF2ADDR		0x13000030
#define BUF1ADDR		(BUF2ADDR+2)

#define Read_buf1()	(*((volatile unsigned char*) BUF1ADDR))
#define Write_buf1(n) 	(*((volatile unsigned char*) BUF1ADDR) = n)

#define Read_buf2()	(*((volatile unsigned char*) BUF2ADDR))
#define Write_buf2(n)	 (*((volatile unsigned char*) BUF2ADDR) = n)
*/
#endif