📄 tx_spdif.vhd
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-------------------------------------------------------------------------- -------- WISHBONE SPDIF IP Core -------- -------- This file is part of the SPDIF project -------- http://www.opencores.org/cores/spdif_interface/ -------- -------- Description -------- SPDIF transmitter. Top level entity for the transmitter -------- core. -------- -------- To Do: -------- - -------- -------- Author(s): -------- - Geir Drange, gedra@opencores.org -------- ------------------------------------------------------------------------------ -------- Copyright (C) 2004 Authors and OPENCORES.ORG -------- -------- This source file may be used and distributed without -------- restriction provided that this copyright statement is not -------- removed from the file and that any derivative work contains -------- the original copyright notice and the associated disclaimer. -------- -------- This source file is free software; you can redistribute it -------- and/or modify it under the terms of the GNU Lesser General -------- Public License as published by the Free Software Foundation; -------- either version 2.1 of the License, or (at your option) any -------- later version. -------- -------- This source is distributed in the hope that it will be -------- useful, but WITHOUT ANY WARRANTY; without even the implied -------- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -------- PURPOSE. See the GNU Lesser General Public License for more -------- details. -------- -------- You should have received a copy of the GNU Lesser General -------- Public License along with this source; if not, download it -------- from http://www.opencores.org/lgpl.shtml -------- ------------------------------------------------------------------------------ CVS Revision History---- $Log: tx_spdif.vhd,v $-- Revision 1.4 2007/10/11 19:14:43 gedra-- Code beautification---- Revision 1.3 2005/03/27 14:03:58 gedra-- Fix: Could not read TxChStat register.---- Revision 1.2 2004/07/20 17:41:25 gedra-- Cleaned up synthesis warnings.---- Revision 1.1 2004/07/19 17:00:38 gedra-- SPDIF transmitter top level.------library ieee;use ieee.std_logic_1164.all;use work.tx_package.all;entity tx_spdif is generic (DATA_WIDTH : integer range 16 to 32; ADDR_WIDTH : integer range 8 to 64; USER_DATA_BUF : integer range 0 to 1; CH_STAT_BUF : integer range 0 to 1); port ( -- Wishbone interface wb_clk_i : in std_logic; wb_rst_i : in std_logic; wb_sel_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_cyc_i : in std_logic; wb_bte_i : in std_logic_vector(1 downto 0); wb_cti_i : in std_logic_vector(2 downto 0); wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0); wb_ack_o : out std_logic; wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Interrupt line tx_int_o : out std_logic; -- SPDIF output signal spdif_tx_o : out std_logic);end tx_spdif;architecture rtl of tx_spdif is signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); signal version_rd : std_logic; signal config_rd, config_wr, status_rd : std_logic; signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0); signal intmask_rd, intmask_wr : std_logic; signal intstat_dout, intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0); signal intstat_rd, intstat_wr : std_logic; signal evt_hsbf, evt_lsbf : std_logic; signal evt_hcsbf, evt_lcsbf : std_logic; signal chstat_dout, chstat_bits : std_logic_vector(DATA_WIDTH - 1 downto 0); signal chstat_rd, chstat_wr : std_logic; signal chstat_freq : std_logic_vector(1 downto 0); signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic; signal mem_wr, mem_rd, ch_status_wr, user_data_wr : std_logic; signal sample_addr : std_logic_vector(ADDR_WIDTH - 2 downto 0); signal sample_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal conf_mode : std_logic_vector(3 downto 0); signal conf_ratio : std_logic_vector(7 downto 0); signal conf_udaten, conf_chsten : std_logic_vector(1 downto 0); signal conf_tinten, conf_txdata, conf_txen : std_logic; signal user_data_a, user_data_b : std_logic_vector(191 downto 0); signal ch_stat_a, ch_stat_b : std_logic_vector(191 downto 0);begin-- Data bus or'ing data_out <= version_dout or config_dout or intmask_dout or intstat_dout or chstat_dout when wb_adr_i(ADDR_WIDTH - 1) = '0' else (others => '0');-- Wishbone bus cycle decoder WB : tx_wb_decoder generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH) port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_sel_i => wb_sel_i, wb_stb_i => wb_stb_i, wb_we_i => wb_we_i, wb_cyc_i => wb_cyc_i, wb_bte_i => wb_bte_i, wb_cti_i => wb_cti_i, wb_adr_i => wb_adr_i, data_out => data_out, wb_ack_o => wb_ack_o, wb_dat_o => wb_dat_o, version_rd => version_rd, config_rd => config_rd, config_wr => config_wr, chstat_rd => chstat_rd, chstat_wr => chstat_wr, intmask_rd => intmask_rd, intmask_wr => intmask_wr, intstat_rd => intstat_rd, intstat_wr => intstat_wr, mem_wr => mem_wr, user_data_wr => user_data_wr, ch_status_wr => ch_status_wr);-- TxVersion - Version register VER : tx_ver_reg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, USER_DATA_BUF => USER_DATA_BUF, CH_STAT_BUF => CH_STAT_BUF) port map ( ver_rd => version_rd, ver_dout => version_dout);-- TxConfig - Configuration register CG32 : if DATA_WIDTH = 32 generate CONF : gen_control_reg generic map ( DATA_WIDTH => 32, ACTIVE_BIT_MASK => "11101111111111110000111100000000") port map ( clk => wb_clk_i, rst => wb_rst_i, ctrl_wr => config_wr, ctrl_rd => config_rd, ctrl_din => wb_dat_i, ctrl_dout => config_dout, ctrl_bits => config_bits); conf_mode(3 downto 0) <= config_bits(23 downto 20); end generate CG32; CG16 : if DATA_WIDTH = 16 generate CONF : gen_control_reg generic map ( DATA_WIDTH => 16,⌨️ 快捷键说明
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