wb_tb_pack.vhd

为提高8051系列单片机I2C总线的工作效率

      write(txt, int_2_hex(DATA, dat_width));
      write(txt, string'(" to addr. "));
      write(txt, int_2_hex(ADDRESS, adr_width));
      wb_adr_o <= std_logic_vector(to_unsigned(ADDRESS, wb_adr_o'length));
      wb_dat_o <= std_logic_vector(to_unsigned(DATA, wb_dat_o'length));
      wb_we_o  <= '1';
      wb_cyc_o <= '1';
      wb_sel_o <= '1';
      -- wait for acknowledge
      wait until rising_edge(wb_clk_i);
      if wb_ack_i /= '1' then
         for i in 1 to WRITE_TIMEOUT loop
            wait until rising_edge(wb_clk_i);
            exit when wb_ack_i = '1';
            if (i = WRITE_TIMEOUT) then
               --write(txt, string'("- @ "));
               --write(txt, now, right, DEFAULT_TIMEWIDTH, DEFAULT_TIMEBASE);
               write (txt, string'("Warning: No acknowledge recevied!"));
            end if;
         end loop;
      end if;
      -- release bus
      wb_adr_o <= WEAK_BUS;
      wb_dat_o <= LOW_BUS;
      wb_we_o  <= 'L';
      wb_cyc_o <= 'L';
      wb_sel_o <= 'L';
      writeline(OUTPUT, txt);
   end;

-- Classic Wishbone read cycle
   procedure wb_read (
      constant ADDRESS   : in  natural;
      variable read_data : out std_logic_vector;
      signal wb_adr_o    : out std_logic_vector;
      signal wb_dat_i    : in  std_logic_vector;
      signal wb_cyc_o    : out std_logic;
      signal wb_sel_o    : out std_logic;
      signal wb_we_o     : out std_logic;
      signal wb_clk_i    : in  std_logic;
      signal wb_ack_i    : in  std_logic) is
      variable txt                  : line;
      variable adr_width, dat_width : natural;
      constant WEAK_BUS             : std_logic_vector(wb_adr_o'range) := (others => 'W');
   begin
      -- determine best width for number printout
      if wb_adr_o'length < 9 then
         adr_width := 2;
      elsif wb_adr_o'length < 17 and wb_adr_o'length > 8 then
         adr_width := 4;
      else
         adr_width := 6;
      end if;
      if wb_dat_i'length < 9 then
         dat_width := 2;
      elsif wb_dat_i'length < 17 and wb_dat_i'length > 8 then
         dat_width := 4;
      else
         dat_width := 8;
      end if;
      -- start cycle on positive edge
      wait until rising_edge(wb_clk_i);
      write(txt, string'("@"));
      write(txt, now, right, TIME_WIDTH);
      wb_adr_o <= std_logic_vector(to_unsigned(ADDRESS, wb_adr_o'length));
      wb_we_o  <= '0';
      wb_cyc_o <= '1';
      wb_sel_o <= '1';
      -- wait for acknowledge 
      wait until rising_edge(wb_clk_i);
      rd_tout  := 0;
      if wb_ack_i /= '1' then
         for i in 1 to READ_TIMEOUT loop
            wait until rising_edge(wb_clk_i);
            exit when wb_ack_i = '1';
            if (i = READ_TIMEOUT) then
               write (txt, string'("Warning: WB_read timeout!"));
               if no_print = 0 then
                  writeline(OUTPUT, txt);
               end if;
               rd_tout := 1;
               errors  := errors + 1;
            end if;
         end loop;
      end if;
      read_data := wb_dat_i;
      if rd_tout = 0 then
         write(txt, string'(" Read "));
         write(txt, slv_2_hex(wb_dat_i));
         write(txt, string'(" from addr. "));
         write(txt, int_2_hex(ADDRESS, adr_width));
         if no_print = 0 then
            writeline(OUTPUT, txt);
         end if;
      end if;
      -- release bus
      wb_adr_o <= WEAK_BUS;
      wb_we_o  <= 'L';
      wb_cyc_o <= 'L';
      wb_sel_o <= 'L';
   end;

-- Check: A read operation followed by a data compare
   procedure wb_check (
      constant ADDRESS  : in  natural;
      constant EXP_DATA : in  natural;
      signal wb_adr_o   : out std_logic_vector;
      signal wb_dat_i   : in  std_logic_vector;
      signal wb_cyc_o   : out std_logic;
      signal wb_sel_o   : out std_logic;
      signal wb_we_o    : out std_logic;
      signal wb_clk_i   : in  std_logic;
      signal wb_ack_i   : in  std_logic) is
      variable txt                  : line;
      variable tout                 : integer;
      variable adr_width, dat_width : natural;
      constant WEAK_BUS             : std_logic_vector(wb_adr_o'range) := (others => 'W');
      variable read_data            : std_logic_vector(wb_dat_i'left downto 0);
   begin
      no_print := 1;                    --  stop read() from printing message
      wb_read (ADDRESS, read_data, wb_adr_o, wb_dat_i, wb_cyc_o, wb_sel_o,
               wb_we_o, wb_clk_i, wb_ack_i);
      no_print := 0;
      -- determine best width for number printout
      if wb_adr_o'length < 9 then
         adr_width := 2;
      elsif wb_adr_o'length < 17 and wb_adr_o'length > 8 then
         adr_width := 4;
      else
         adr_width := 6;
      end if;
      if wb_dat_i'length < 9 then
         dat_width := 2;
      elsif wb_dat_i'length < 17 and wb_dat_i'length > 8 then
         dat_width := 4;
      else
         dat_width := 8;
      end if;
      write(txt, string'("@"));
      write(txt, now, right, TIME_WIDTH);

      if rd_tout = 0 then
         if read_data = std_logic_vector(to_unsigned(EXP_DATA, wb_dat_i'length)) then
            write(txt, string'(" Check "));
            write(txt, slv_2_hex(wb_dat_i));
            write(txt, string'(" at addr. "));
            write(txt, int_2_hex(ADDRESS, adr_width));
            write(txt, string'(" - OK!"));
         else
            write(txt, string'(" Check failed at addr. "));
            write(txt, int_2_hex(ADDRESS, adr_width));
            write(txt, string'("! Got "));
            write(txt, slv_2_hex(wb_dat_i));
            write(txt, string'(", expected "));
            write(txt, int_2_hex(EXP_DATA, dat_width));
            errors := errors + 1;
         end if;
         writeline(OUTPUT, txt);
      else
         write(txt, string'(" Read timeout from addr. "));
         write(txt, int_2_hex(ADDRESS, adr_width));
         write(txt, string'(" during check!"));
         writeline(OUTPUT, txt);
      end if;
   end;

-- display a message with time stamp
   procedure message (
      constant MSG : in string) is
      variable txt : line;
   begin
      write(txt, string'("@"));
      write(txt, now, right, TIME_WIDTH);
      write(txt, string'(" -- ") & MSG);
      writeline(OUTPUT, txt);
   end;

-- wait for event to happen, with timeout
   procedure wait_for_event (
      constant MSG     : in string;        -- message
      constant TIMEOUT : in time;          -- timeout
      signal trigger   : in std_logic) is  -- trigger signal
      variable txt : line;
      variable t1  : time;
   begin
      t1 := now;
      wait on trigger for timeout;
      write(txt, string'("@"));
      write(txt, now, right, TIME_WIDTH);
      write(txt, string'(" "));
      write(txt, MSG);
      if now - t1 >= TIMEOUT then
         write(txt, string'(" - Timed out!"));
         errors := errors + 1;
      else
         write(txt, string'(" - OK!"));
      end if;
      writeline(OUTPUT, txt);
   end;

-- check signal value
   procedure signal_check (
      constant MSG   : in string;        -- signal name
      constant VALUE : in std_logic;     -- expected value
      signal sig     : in std_logic) is  -- signal to check
      variable txt : line;
   begin
      write(txt, string'("@"));
      write(txt, now, right, TIME_WIDTH);
      write(txt, string'(" "));
      write(txt, MSG);
      write(txt, string'(" "));
      if sig = VALUE then
         write(txt, string'("verified to be "));
      else
         write(txt, string'("has incorrect value! Expected "));
         errors := errors + 1;
      end if;
      if VALUE = '1' then
         write(txt, string'("1!"));
      else
         write(txt, string'("0!"));
      end if;
      writeline(OUTPUT, txt);
   end;

-- Report number of errors encountered during simulation
   procedure sim_report (
      constant MSG : in string) is
      variable txt : line;
   begin
      write(txt, string'("@"));
      write(txt, now, right, TIME_WIDTH);
      write(txt, string'(" Simulation completed with "));
      write(txt, errors);
      write(txt, string'(" errors!"));
      writeline(OUTPUT, txt);
   end;

-- check vector value
   procedure vector_check (
      constant MSG   : in string;               -- signal name
      constant VALUE : in std_logic_vector;     -- expected value
      signal sig     : in std_logic_vector) is  -- signal to check
      variable txt : line;
   begin
      write(txt, string'("@"));
      write(txt, now, right, TIME_WIDTH);
      write(txt, string'(" "));
      write(txt, MSG);
      write(txt, string'(" "));
      if sig = VALUE then
         write(txt, string'("verified to be "));
      else
         write(txt, string'("has incorrect value! Expected "));
         write(txt, slv_2_hex(VALUE));
         write(txt, string'(", but got "));
         errors := errors + 1;
      end if;
      write(txt, slv_2_hex(sig));
      writeline(OUTPUT, txt);
   end;
   
end wb_tb_pack;