liushuideng.v

代码为verilog编写的流水等程序

module	clk_led(clk,q_out);
input	clk;
output	[7:0]q_out;
reg		[15:0]cout;
reg		[7:0]q;
reg		[7:0]q_out;
//initial 
		//q=8'b1111_1111;
always @(posedge clk)
	begin	
	 cout<=cout+1;
		if(cout==16'b1111_1111_1111_1111)
			begin 
				cout<=0;
				q<=q>>1;
					if(q==8'b0000_0000)
					q=8'b1111_1111;
			end	
			q_out<=q[7:0];
	end
endmodule