📄 nic.c
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#include <p18cxxx.h>
#include <usart.h>
#include <delays.h>
#include "sockets.h"
#include "ioports.h"
/*
#define dataport PORTD
#define addrport PORTB
#define cntlport PORTE
#define IOR PORTEbits.RE0
#define IOW PORTEbits.RE1
#define RESET PORTEbits.RE2
#define AEN PORTBbits.RB4
#define LE PORTCbits.RC1
#define writedataport(datum) PORTD=datum;
#define writeaddrport(datum) PORTB=datum | 0xF0;
#define readdataport PORTD
#define dataport_out TRISD=0x00
#define dataport_in TRISD=0xFF
#define PORTADigitalIO ADCON1=0x07
#define initTRISRegisters TRISA=0x00;TRISB=0xE0;TRISC=0xBD;TRISD=0x00;TRISE=0x00;
*/
#define clr_reset RESET=0
#define clr_ior IOR=0
#define clr_iow IOW=0
#define clr_aen AEN=0
#define set_reset RESET=1
#define set_ior IOR=1
#define set_iow IOW=1
#define set_aen AEN=1
#define latchdata LE=1; \
Delay10TCYx(1); \
LE=0;
#define set_hex hexflag=1
#define clr_hex hexflag=0
//******************************************************************
//* RpppL (Read packetpage port Low)
//* Reads low byte of specified PacketPage Port
//* pp_port = PacketPage Port - dest = where to store data
//******************************************************************
#define RpppL(pp_port,dest) writeaddrport(pp_port); \
clr_aen; \
clr_ior; \
Nop() \
dest = readdataport; \
set_ior; \
set_aen;
//******************************************************************
//* RpppH (read packetpage port High)
//* Reads high byte of specified PacketPage Port
//* pp_port = PacketPage Port - dest = where to store data
//******************************************************************
#define RpppH(pp_port,dest) writeaddrport(pp_port+1); \
clr_aen; \
clr_ior; \
Nop() \
dest = readdataport; \
set_ior; \
set_aen;
//******************************************************************
//* WpppL (Write packetpage port Low)
//* Writes low byte to specified PacketPage Port
//* pp_port = PacketPage Port - datum = data to write
//******************************************************************
#define WpppL(pp_port,datum) writeaddrport(pp_port); \
writedataport(datum); \
clr_aen; \
clr_iow; \
Nop() \
set_iow; \
set_aen;
//******************************************************************
//* WpppH (Write packetpage port High)
//* Writes high byte to specified PacketPage Port
//* pp_port = PacketPage Port - datum = data to write
//******************************************************************
#define WpppH(pp_port,datum) writeaddrport(pp_port+1); \
writedataport(datum) ; \
clr_aen; \
clr_iow; \
Nop() \
set_iow; \
set_aen;
//******************************************************************
//* PacketPage I/O Port Definitions
//******************************************************************
#define pageport_RxTxData0 0x00 //Receive/Transmit data Port 0
#define pageport_RxTxData1 0x02 //Receive/Transmit data Port 1
#define pageport_TxCmd 0x04 //Transmit Command
#define pageport_TxLen 0x06 //Transmit Length
#define pageport_ISQ 0x08 //Interrupt Status Queue
#define pageport_Ptr 0x0A //PacketPage Pointer
#define pageport_Data0 0x0C //PacketPage Data Port 0
#define pageport_Data1 0x0E //PacketPage Data Port 1
//******************************************************************
//* PacketPage Internal Register Definitions
//******************************************************************
#define ppageEISA 0x0000 //EISA Registration number of CS8900
#define ppagePID 0x0002 //Product ID Number
#define ppageBaseIO 0x0020 //I/O Base Address
#define ppageINT 0x0022 //Interrupt number (0,1,2, or 3)
#define ppageBaseMemory 0x002C //20-bit Memory Base address register
#define ppageRxCFG 0x0102 //Receiver Configuration
#define ppageRxCTL 0x0104 //Receiver Control
#define ppageTxCFG 0x0106 //Transmit Configuration
#define ppageTxCmdRO 0x0108 //Transmit Command Read Only Status
#define ppageBufCFG 0x010A //Buffer Configuration
#define ppageLineCTL 0x0112 //Line Control
#define ppageSelfCTL 0x0114 //Self Control
#define ppageBusCTL 0x0116 //Bus Control
#define ppageTestCTL 0x0118 //Test Control
#define ppageISQ 0x0120 //Interrupt status queue
#define ppageRxEvent 0x0124 //Receiver Event
#define ppageTxEvent 0x0128 //Transmitter Event
#define ppageBufEvent 0x012C //Buffer Event
#define ppageRxMiss 0x0130 //Receiver Miss Counter
#define ppageTxColl 0x0132 //Transmit Collision Counter
#define ppageLineStatus 0x0134 //Line Status
#define ppageSelfStatus 0x0136 //Self Status
#define ppageBusStatus 0x0138 //Bus Status
#define ppageTxCmd 0x0144 //Transmit Command Request
#define ppageTxLength 0x0146 //Transmit Length
#define ppageIA 0x0158 //Individual Address
#define ppageRxStatus 0x0400 //Receive Status
#define ppageRxLength 0x0402 //Receive Length
#define ppageRxFrame 0x0404 //Receive Frame Offset
#define ppageTxFrame 0x0A00 //Transmit Frame Offset
//******************************************************************
//******************************************************************
//* PacketPage Configuration and Control Register Definitons
//******************************************************************
//******************************************************************
//******************************************************************
//* PacketPage Event Register Definitions
//******************************************************************
#define RXEVENT_REG 0x0004
#define TXEVENT_REG 0x0008
#define BUFEVENT_REG 0x000C
#define RXMISS_REG 0x0010
#define TXCOLL_REG 0x0012
//******************************************************************
//* PacketPage Receiver Configuration Bit Definitions
//******************************************************************
#define RXCFG_NOBUF_CRC 0x0000
#define RXCFG_SKIP_BIT 0x0006
#define RXCFG_SKIP 0x0040
#define RXCFG_RX_OK_IE 0x0100
#define RXCFG_CRC_ERR_IE 0x1000
#define RXCFG_RUNT_IE 0x2000
#define RXCFG_X_DATA_IE 0x4000
//******************************************************************
//* PacketPage Receiver Control Register Bit Definitions
//******************************************************************
#define RXCTL_SETUP (RXCTL_RX_OK_A|RXCTL_IND_A|RXCTL_BCAST_A)
#define RXCTL_RX_OK_A 0x0100
#define RXCTL_MCAST_A 0x0200
#define RXCTL_IND_A 0x0400
#define RXCTL_BCAST_A 0x0800
#define RXCTL_CRC_ERR_A 0x1000
#define RXCTL_RUNT_A 0x2000
#define RXCTL_X_DATA_A 0x4000
//******************************************************************
//* PacketPage Transmit Configuration Register Bit Definitions
//******************************************************************
#define TXCFG_LOSS_CRS_IE 0x0040
#define TXCFG_SQE_ERR_IE 0x0080
#define TXCFG_TX_OK_IE 0x0100
#define TXCFG_OUT_WIN_IE 0x0200
#define TXCFG_JABBER_IE 0x0400
#define TXCFG_16_COLL_IE 0x8000
#define TXCFG_ALL_IE 0x8FC0
//******************************************************************
//* PacketPage Transmit Command Register Bit Definitions
//******************************************************************
#define TXCMD_AFTER_5 0x0000
#define TXCMD_AFTER_381 0x0080
#define TXCMD_AFTER_1021 0x0040
#define TXCMD_AFTER_ALL 0x00C0
#define TXCMD_FORCE 0x0100
#define TXCMD_ONE_COLL 0x0200
#define TXCMD_NO_CRC 0x1000
#define TXCMD_NO_PAD 0x2000
//******************************************************************
//* PacketPage Buffer Configuration Register Bit Definitions
//******************************************************************
#define BUFCFG_SW_INT 0x0040
#define BUFCFG_RDY4TX_IE 0x0100
#define BUFCFG_TX_UNDR_IE 0x0200
//******************************************************************
//* PacketPage Line Control Bit Definitions
//******************************************************************
#define LINECTL_RX_ON_BIT 0x0006
#define LINECTL_RX_ON 0x0040
#define LINECTL_TX_ON_BIT 0x0007
#define LINECTL_TX_ON 0x0080
#define LINECTL_AUI_ONLY 0x0100
#define LINECTL_10BASET 0x0000
//******************************************************************
//* PacketPage Self Control Register Bit Definitions
//******************************************************************
#define SELFCTL_RESET 0x0040
#define SELFCTL_HC1E 0x2000
#define SELFCTL_HCB1 0x8000
//******************************************************************
//* PacketPage Bus Control Bit Definitions
//******************************************************************
#define BUSCTL_USE_SA 0x0200
#define BUSCTL_MEM_MODE 0x0400
#define BUSCTL_IOCHRDY 0x1000
#define BUSCTL_INT_ENBL_BIT 0x0007
#define BUSCTL_INT_ENBL 0x8000
//******************************************************************
//* PacketPage Test Control Bit Definitions
//******************************************************************
#define TESTCTL_DIS_LT 0x0080
#define TESTCTL_ENDEC_LP 0x0200
#define TESTCTL_AUI_LOOP 0x0400
#define TESTCTL_DIS_BKOFF 0x0800
#define TESTCTL_FDX 0x4000
//******************************************************************
//******************************************************************
//* PacketPage Status and Event Register Definitons
//******************************************************************
//******************************************************************
//******************************************************************
//* PacketPage Receiver Event Register Bit Definitions
//******************************************************************
#define RXEVENT_RX_OK 0x0100
//#define RXEVENT_RX_OK_BIT 0x0000
#define RXEVENT_RX_OK_BIT 0x0008
#define RXEVENT_IND_ADDR 0x0800
#define RXEVENT_CRC_ERR 0x1000
#define RXEVENT_RUNT 0x0000
#define RXEVENT_X_DATA 0x4000
//******************************************************************
//* PacketPage Transmit Event Register Bit Definitions
//******************************************************************
#define TXEVENT_TX_OK 0x0100
#define TXEVENT_OUT_WIN 0x0200
#define TXEVENT_JABBER 0x0400
#define TXEVENT_16COLLS 0x1000
//******************************************************************
//* PacketPage Self Status Bit Definitions
//******************************************************************
#define SELFSTAT_INIT_DONE_BIT 0x0007
#define SELFSTAT_INIT_DONE 0x0080
#define SELFSTAT_SI_BUSY 0x0100
#define SELFSTAT_EEP_PRES 0x0200
#define SELFSTAT_EEP_OK 0x0400
#define SELFSTAT_EL_PRES 0x0800
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