audio.tci

TI官方演示程序

/*
 *  ======== audio.tci ========
 *
 *! Revision History
 *! ================
 *! 10-Oct-2001 df	Changed PIP buffer alignment to work with cache.
 *! 29-Aug-2001 kw	Updated with new names 'pipTx', 'swiEcho', etc.
 *! 02-Jul-2001 ar	Added comments and remove a heap usage.
 *! 22-Jun-2001 ar/skd  Created.
 */

/* Board should be running at 160 Mhz */
GBL.CLKOUT = 160.0000;

/* Configures board to run at 160 Mhz ( (9 + 1) * 16.0 Mhz crystal) */
GBL.CLKMD = 0x9007;

/*
 * ======== trace ========
 */
var trace = LOG.create("trace");
trace.bufLen = 512;

/*
 * ======== LOG_sytem ========
 */
LOG_system.bufLen = 512;


/*
 * ======== swiEcho ========
 */
var swiEcho = SWI.create("swiEcho");
swiEcho["fxn"] = prog.decl("echo");
swiEcho.mailbox = 3;

/*
 * ======== pipRx ========
 */
var pipRx = PIP.create("pipRx");
pipRx.bufAlign = 128; 
pipRx.frameSize = 256;
pipRx.numFrames = 2; 
pipRx.monitor = "reader"; 
pipRx.notifyWriterFxn = prog.decl("PLIO_rxPrime");
pipRx.notifyWriterArg0 = prog.decl("plioRx");
pipRx.notifyReaderFxn = prog.decl("SWI_andn");
pipRx.notifyReaderArg0 = prog.decl("swiEcho");
pipRx.notifyReaderArg1 = 0x1;

/*
 * ======== pipTx ========
 */
var pipTx = PIP.create("pipTx");
pipTx.bufAlign = 128; 
pipTx.frameSize = 256;
pipTx.numFrames = 2; 
pipTx.monitor = "writer"; 
pipTx.notifyWriterFxn = prog.decl("SWI_andn");
pipTx.notifyWriterArg0 = prog.decl("swiEcho");
pipTx.notifyWriterArg1 = 0x2;
pipTx.notifyReaderFxn = prog.decl("PLIO_txPrime");
pipTx.notifyReaderArg0 = prog.decl("plioTx");

/*
 *  ======== eliminate unused components ========
 */
TSK.ENABLETSK = 0;                         /* don't use TSK threads */

/* remove all use of heaps */
MEM.BIOSOBJSEG = MEM_NULL;
MEM.MALLOCSEG = MEM_NULL;
var memObjs = MEM.instances();
for (var i = 0; i < memObjs.length; i++ ) {
    if (memObjs[i] != MEM_NULL) {   /* can't remove heap from MEM_NULL */
	if (memObjs[i].createHeap != 0) {
	    memObjs[i].createHeap = 0;
	}
    }
}