initpcm3002.asm

用于DSK5416的程序

**********************************************************************
*
* initPCM3002.asm
*
* This module initializes the PCM3002 codec on the C5416 DSK.
*
* Author:       Avtar Singh, SJSU
*
**********************************************************************

                .include    "regs.asm"
                .def        initPCM3002
                .def        sampling_rate_set

                   
* Define values for the codec clock register (in the CPLD) and
* the control registers of the PCM3002 codec.

                ; Codec clock Register (0000 1010)
                    
                ; Bit7-4 = 0000: Reserved
                ; Bit3 = 1: Clock divisor selected
                ;        0: No divisor, 48 KHz sampling rate
                ; Bit2 = 0: Clock enabled
                ; Bit1-0 = 00: Clock divisor for 24 KHz sampling rate
                ;          01: Clock divisor for 12 KHz sampling rate
                ;          10: Clock divisor for 8 KHz sampling rate
                ;          11: Clock divisor for 6 KHz sampling rate
                    
VAL_CLK_REG     .set        12h


                ; Register 0 (0000 0001 1111 1111)
                ; Bit15-11 = 00000: Reserved
                ; Bit10-9 = 00: Register address 0
                ; Bit8 = 1: Enable DAC attenuation data LDL
                ; Bit7-0 = 11111111: 0 dB left channel attenuation
                   
VAL_REG0        .set        01ffh

                    
                ; Register 1 (0000 0011 1111 1111)
                    
                ; Bit15-11 = 00000: Reserved
                ; Bit10-9 = 01: Register address 1
                ; Bit8 = 1: Enable DAC attenuation data LDR
                ; Bit7-0 = 11111111: 0 dB right channel attenuation
                    
VAL_REG1        .set        03ffh

                    
                ; Register 2 (0000 0100 1000 0010)
                    
                ; Bit15-11 = 00000: Reserved
                ; Bit10-9 = 10: Register address 2
                ; Bit8 = 0: Disable ADC power-down control (PDAD)
                ; Bit7 = 1: Bypass high-pass filter
                ; Bit5 = 0: Individual channel attenuation control
                ; Bit4 = 0: Infinite zero detection disabled
                ; Bit3 = 0: DAC outputs enabled
                ; Bit2-1 = 01: De-emphasis off
                ; Bit0 = 0: Mute disabled
                    
VAL_REG2        .set        0482h

                    
                ; Register 3 (0000 0110 0000 1000)
                    
                ; Bit15-11 = 00000: Reserved
                ; Bit10-9 = 11: Register address 3
                ; Bit8-6 = 000: Reserved
                ; Bit5 = 0: Loop-back disabled
                ; Bit4 = 0: Reserved
                ; Bit3-2 = 10: Format 2
                ; Bit1 = 0: Left is H, Right is L
                ; Bit0 = 0: Reserved
                   
VAL_REG3        .set        0608h

                 

                .text
                    
* This procedure initializes the PCM3002 codec on the C5416 DSK via the CPLD.
* The procedure uses location 60h as scratch pad


initPCM3002:
                portr       DSK_CPLD_MISC, 60h      ; Select codec
                andm        #0FFFEh, 60h            
                portw       60h, DSK_CPLD_MISC
              
                call        sampling_rate_set       ; Set Sampling rate

                ld          #VAL_REG0, A            ; Program codec reg0
                call        CPLD_write
                    
                ld          #VAL_REG1, A            ; Program codec reg1
                call        CPLD_write
                    
                ld          #VAL_REG2, A            ; Program codec reg2
                call        CPLD_write
                    
                ld          #VAL_REG3, A            ; Program codec reg3
                call        CPLD_write

                ret



* This procedure sets the clock for the PCM3002 codec.
* The following sequence is specified:
* 
* 1. Set the CLK_STOP bit to 1.
* 2. Set the CLK_DIV1 and CLK_DIV0 bits to the sampling rate value, keeping
*    the CLK_STOP bit as 1.
* 3. Reset the CLK_STOP bit to 0.
* 4. Set the DIV_SEL bit to 1.
*
* Enter with A = #VAL_CLK_REG to specify the sampling rate.
*
* The procedure uses location 60h as scratch pad

                   
sampling_rate_set:
                portr       DSK_CPLD_CODEC_CLK, 60h ; Stop the clock            
                orm         #04h, 60h               
                portw       60h, DSK_CPLD_CODEC_CLK
                    
                ld          #VAL_CLK_REG, A         ; Get Sample rate value
                bc          NoDivisor, AEQ          ; Check if highest rate
                    
                and         #03h, A                 ; Select the divisor bits
                or          #04h, A                 ; Keep the clock stopped
                stl         A, 60h                  ; Set the clock divisor
                portw       60h, DSK_CPLD_CODEC_CLK
                    
                andm        #0FBh, 60h              ; Resume the clock
                portw       60h, DSK_CPLD_CODEC_CLK
                    
                orm         #08h, 60h               ; Select the divisor
                portw       60h, DSK_CPLD_CODEC_CLK
                    
                b           sampling_rate_done
                    
NoDivisor:
                st          #00h, 60h               ; Resume the clock
                portw       60h, DSK_CPLD_CODEC_CLK
                   
sampling_rate_done:
                ret



* This procedure transmits a 16-bit control word to the PCM3002 via the CPLD.
* The procedure uses location 60h as scratch pad
*
* Argument A: 16-bit control word

                 
CPLD_write:
                stl         A, 60h                  ; Write low control byte
                portw       60h, DSK_CPLD_CODEC_L
                    
                stl         A, -8, 60h              ; write high control byte
                portw       60h, DSK_CPLD_CODEC_H

CODEC_WAIT:
                portr       DSK_CPLD_MISC, 60h
                andm        #80h, 60h               ; Get the CODEC_RDY bit
                ld          60h, A
                bc          CODEC_WAIT, ANEQ        ; wait till all bits sent

                ret