initmcbsp2.asm

用于DSK5416的程序

*********************************************************************************
*
* initMcBSP2.asm
*
* This module initializes the serial port McBSP2 on the C5416 DSK.
*
* Author:       Avtar Singh, SJSU
*
*********************************************************************************

                .include    "regs.asm"
                .def        initMcBSP2
                   

* Define the default values for the registers of McBSP2.

                ; Serial Port Control Register 1 (0010 0000 0010 0000)
                   
                ; Bit15 = 0: Digital loopback disabled
                ; Bit14-13 = 01: Right-justify, sign extend
                ; Bit12-11 = 00: Clock stop disabled
                ; Bit10-8 = 00: Reserved
                ; Bit7 = 0: DX enabler off
                ; Bit6 = 0: A-bis mode disabled
                ; Bit5-4 = 10: RINT driven by frame sync
                ; Bit3 = 0: No sync error
                ; Bit2 = 0: RBRs not in overrun condition
                ; Bit1 = 0: Receiver not ready
                ; Bit0 = 0: Receiver in disabled and in reset state
                    
VAL_SPCR1       .set        2020h

                    
                ; Serial Port Control Register 2 (0000 0000 0000 0000)
                    
                ; Bit15-10: = 00h: Reserved
                ; Bit9 = 0: Free running mode disabled
                ; Bit8 = 0: Soft mode disabled
                ; Bit7 = 0: Frame sync not generated
                ; Bit6 = 0: Disable sample rate generator
                ; Bit5-4 = 00: XINT driven by XRDY
                ; Bit3 = 0: No sync error
                ; Bit2 = 0: XSRs empty
                ; Bit1 = 0: Transmitter not ready
                ; Bit0 = 0: Transmitter in disabled and in reset state
                   
VAL_SPCR2       .set        0000h

                    
                ; Receive Control Register 1 (0000 0000 0110 0000)
                    
                ; Bit15 = 0: Reserved
                ; Bit14-8 = 0000000: 1 word per frame
                ; Bit7-5 = 011: 20 bit receive word
                ; Bit4-0 = 00000: Reserved
                   
VAL_RCR1        .set        0060h
    
                    
                ; Receive Control Register 2 (0000 0000 0110 0001)
                
                ; Bit15 = 0: Single phase frame
                ; Bit14-8 = 00h: 1 word per frame
                ; Bit7-5 = 011: 20 bit receive word
                ; Bit4-3 = 00: No companding
                ; Bit2 = 0: Receive frame sync pulses not ignored
                ; Bit1-0 = 01: 1-bit data delay
                    
VAL_RCR2        .set        0061h


                ; Transmit Control Register 1 (0000 0000 0110 0000)
                  
                ; Bit15 = 0: Reserved
                ; Bit14-8 = 00h: 1 word per frame
                ; Bit7-5 = 011: 20 bit transmit word
                ; Bit4-0 = 0h: Reserved
                    
VAL_XCR1        .set        0060h
    
                   
                ; Transmit Control Register 2 (0000 0000 0110 0000)
                    
                ; Bit15 = 0: Single phase frame
                ; Bit14-8 = 00h: 1 word per frame
                ; Bit7-5 = 011: 20 bit transmit word
                ; Bit4-3 = 00: No companding
                ; Bit2 = 0: Transmit frame sync pulses not ignored
                ; Bit1-0 = 00: 0-bit data delay
                   
VAL_XCR2        .set        0060h
    
                    
                ; Pin Control Register (0000 0000 0000 1100)
                    
                ; Bit15-14 = 00: Reserved
                ; Bit13 = 0: DX, FSX, and CLKX are seial port pins
                ; Bit12 = 0: DR, FSR, CLKR, and CLKS are serial port pins
                ; Bit11 = 0: External transmit frame sync
                ; Bit10 = 0: External receive frame sync
                ; Bit9 = 0: External transmit clock
                ; Bit8 = 0: External receive clock
                ; Bit7 = 0: Reserved
                ; Bit6 = 0: CLKS status
                ; Bit5 = 0: DX status
                ; Bit4 = 0: DR status
                ; Bit3 = 1: FSX active high
                ; Bit2 = 1: FSR active high
                ; Bit1 = 0: Transmit data sampled on rising edge of CLKX
                ; Bit0 = 0: Receive data sampled on rising edge of CLKR
                    
VAL_PCR         .set        000Ch




* This procedure initializes the McBSP2 for use with the PCM3002 codec on the
* C5416 DSK.

                .text
                    
initMcBSP2:
                stm         #SPCR1, MCBSP2_SPSA           ; Disable McBSP2 RX
                ldm         MCBSP2_SPSD, A
                and         #0FFFEh, A
                stlm        A, MCBSP2_SPSD

                stm         #SPCR2, MCBSP2_SPSA           ; Disable McBSP2 TX
                ldm         MCBSP2_SPSD, A
                and         #0FFFEh, A
                stlm        A, MCBSP2_SPSD

                stm         #SPCR1, MCBSP2_SPSA           ; Set SPCR1
                stm         #VAL_SPCR1, MCBSP2_SPSD

                stm         #SPCR2, MCBSP2_SPSA           ; Set SPCR2
                stm         #VAL_SPCR2, MCBSP2_SPSD

                stm         #RCR1, MCBSP2_SPSA            ; Set RCR1
                stm         #VAL_RCR1, MCBSP2_SPSD

                stm         #RCR2, MCBSP2_SPSA            ; Set RCR2
                stm         #VAL_RCR2, MCBSP2_SPSD

                stm         #XCR1, MCBSP2_SPSA            ; Set XCR1
                stm         #VAL_XCR1, MCBSP2_SPSD

                stm         #XCR2, MCBSP2_SPSA            ; Set XCR2
                stm         #VAL_XCR2, MCBSP2_SPSD

                stm         #PCR, MCBSP2_SPSA             ; Set PCR
                stm         #VAL_PCR, MCBSP2_SPSD

                ret