two_ask.vhd

2ask调制与解调包含顶层文件

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity two_ask is
        port ( base :  in   std_logic;
	          reset:  in   std_logic;
			clk  :  in   std_logic;
			y    :  out  std_logic_vector(7 downto 0);
		   sin_out:  out  std_logic_vector(7 downto 0));

end two_ask;

architecture Behavioral of two_ask is
      component sin_rom  is
	           port ( addr: in  std_logic_vector(5 downto 0);
	                     q: out std_logic_vector(7 downto 0));
	 end component;
	 
	 signal sin :            std_logic_vector(7 downto 0);
	 signal address:         std_logic_vector(5 downto 0);
begin

  rom_map: sin_rom 
               port map(  addr   =>  address,
                          q      =>   sin);

               sin_out   <=    sin;


     process(clk)
	  begin     
		  if clk'event and clk = '1'then
		       if reset   =  '1' then
			      address <= "000000";
			  else
			      address <= address + 1;
                 end if;
            end if;

     end process;

    process( sin,base)

	  begin
	   
	    if base = '1' then
	        
		   y  <= 	 sin ;

         else 
	       
		  y   <=   conv_std_logic_vector(130,8);
		  
	    end if; 

	  
    end process;


end Behavioral;