two_ask_test.vhd

2ask调制与解调包含顶层文件

-- VHDL Test Bench Created from source file two_ask.vhd -- 17:17:28 04/04/2008
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY two_ask_test IS
END two_ask_test;

ARCHITECTURE behavior OF two_ask_test IS 

	COMPONENT two_ask
	PORT(
		base : IN std_logic;
		reset : IN std_logic;
		clk : IN std_logic;          
		y : OUT std_logic_vector(7 downto 0);
		sin_out :out std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	SIGNAL base :  std_logic;
	SIGNAL reset :  std_logic;
	SIGNAL clk :  std_logic;
	SIGNAL y :  std_logic_vector(7 downto 0);
	signal sin_out : std_logic_vector(7 downto 0);
BEGIN

	uut: two_ask PORT MAP(
		base => base,
		reset => reset,
		clk => clk,
		y => y,
		sin_out => sin_out
	);


 PROCESS
   BEGIN

	 reset  <=  '1';
      wait for 20 ns;

	 reset  <=  '0';
	 wait for 50000 ns;
   END PROCESS;

    PROCESS
   BEGIN

	 clk  <=  '1';
      wait for 10 ns;

	 clk  <=  '0';
	 wait for 10 ns;
   END PROCESS;

    process
      begin
	   
	 base  <= '1';
	 wait for 4820 ns;
	 
	 base  <= '0';
	 wait for 3840 ns;

	 base  <= '1';
	 wait for 7680 ns;

	 base  <= '0';
	 wait for 7680 ns;

      base  <= '1';
	 wait for 3840 ns;
   
   end process;


END;