sin_rom.vhd

2ask调制与解调包含顶层文件

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.rom.all;
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sin_rom is
       port ( addr: in  std_logic_vector(5 downto 0);
	            q: out std_logic_vector(7 downto 0));
end sin_rom;

architecture Behavioral of sin_rom is

begin
	q<= conv_std_logic_vector(rom(conv_integer(addr)),8);

end Behavioral;