rf_ntrx.h

6lowPan的协议栈

	TRX_REG_Version = 0x01,
	TRX_REG_Revision = 0x02,
	TRX_REG_DioInValueAlarmStatus = 0x04,
	TRX_REG_TxIrqStatus = 0xf,
	TRX_REG_RxIrqStatus = 0xf,
	TRX_REG_BbTimerIrqStatus = 0xf,
	TRX_REG_LoIrqStatus = 0xf,
	TRX_REG_TxIntsRawStat = 0x10,
	TRX_REG_RxIntsRawStat = 0x11,
	TRX_REG_LoIntsRawStat = 0x12,
	TRX_REG_AgcGain = 0x26,
	TRX_REG_ToaOffsetMeanDataValid = 0x2b,
	TRX_REG_PhaseOffsetData = 0x2e,
	TRX_REG_PhaseOffsetAck = 0x2e,
	TRX_REG_ToaOffsetMeanAckValid = 0x30,
	TRX_REG_RxPacketType = 0x31,
	TRX_REG_RxAddrMatch = 0x31,
	TRX_REG_RxCrc1Stat = 0x31,
	TRX_REG_RxCrc2Stat = 0x31,
	TRX_REG_RxCorrBitErr = 0x32,
	TRX_REG_RxCorrErrThres = 0x32,
	TRX_REG_RxAddrSegEsMatch = 0x33,
	TRX_REG_RxAddrSegIsMatch = 0x33,
	TRX_REG_RxCryptEn = 0x33,
	TRX_REG_RxCryptId = 0x33,
	TRX_REG_RxCryptSeqN = 0x33,
	TRX_REG_RxTimeSlotControl = 0x37,
	TRX_REG_TxArqCnt = 0x3c,
	TRX_REG_DebugMacRxCmd = 0x7d,
	TRX_REG_DebugMacTxCmd = 0x7d,
	TRX_REG_DebugMacFsm = 0x7e,
	TRX_REG_DebugMacTxRxCtrl = 0x7e,
	TRX_REG_DebugBitProcFsm = 0x7f,
	TRX_REG_DebugBitProcTx = 0x7f,
	TRX_REG_DebugBitProcRx = 0x7f,
	TRX_REG_DebugRxDetStatus = 0x7f,
	TRX_REG_ToaOffsetMeanData = 0x7f,
	TRX_REG_TxRespTime = 0x7f,
	TRX_REG_ToaOffsetMeanAck = 0x7f
} NTRX_RO_REG;

typedef enum{
	NTRX_SpiBitOrder_MASK = 0x01,
	NTRX_SpiTxDriver_MASK = 0x01 << NA_SpiTxDriver_B,
	NTRX_IrqPolarity_MASK = 0x01 << NA_IrqPolarity_B,
	NTRX_IrqDriver_MASK = 0x01 << NA_IrqDriver_B,
	NTRX_Version_MASK = 1,
	NTRX_WakeUpTimeByte_MASK = 0xff,
	NTRX_Revision_MASK = 1,
	NTRX_WakeUpTimeWe_MASK = 0x07 << NA_WakeUpTimeWe_LSB,
	NTRX_BattMgmtEnable_MASK = 0x01 << NA_BattMgmtEnable_B,
	NTRX_BattMgmtThreshold_MASK = 0x0f << NA_BattMgmtThreshold_LSB,
	NTRX_BattMgmtCompare_MASK = 0x01 << NA_BattMgmtCompare_B,
	NTRX_DioDirection_MASK = 0x01 << NA_DioDirection_B,
	NTRX_DioOutValueAlarmEnable_MASK = 0x01 << NA_DioOutValueAlarmEnable_B,
	NTRX_DioAlarmStart_MASK = 0x01 << NA_DioAlarmStart_B,
	NTRX_DioAlarmPolarity_MASK = 0x01 << NA_DioAlarmPolarity_B,
	NTRX_DioUsePullup_MASK = 0x01 << NA_DioUsePullup_B,
	NTRX_DioUsePulldown_MASK = 0x01 << NA_DioUsePulldown_B,
	NTRX_DioInValueAlarmStatus_MASK = 0x0f << NA_DioInValueAlarmStatus_LSB,
	NTRX_DioPortWe_MASK = 0x0f << NA_DioPortWe_LSB,
	NTRX_EnableWakeUpRtc_MASK = 0x01 << NA_EnableWakeUpRtc_B,
	NTRX_EnableWakeUpDio_MASK = 0x01 << NA_EnableWakeUpDio_B,
	NTRX_PowerUpTime_MASK = 0x07 << NA_PowerUpTime_LSB,
	NTRX_PowerDownMode_MASK = 0x01 << NA_PowerDownMode_B,
	NTRX_PowerDown_MASK = 0x01 << NA_PowerDown_B,
	NTRX_ResetBbClockGate_MASK = 0x01 << NA_ResetBbClockGate_B,
	NTRX_ResetBbRadioCtrl_MASK = 0x01 << NA_ResetBbRadioCtrl_B,
	NTRX_EnableBbCrystal_MASK = 0x01 << NA_EnableBbCrystal_B,
	NTRX_EnableBbClock_MASK = 0x01 << NA_EnableBbClock_B,
	NTRX_BypassBbCrystal_MASK = 0x01 << NA_BypassBbCrystal_B,
	NTRX_FeatureClockFreq_MASK = 0x07 << NA_FeatureClockFreq_LSB,
	NTRX_EnableFeatureClock_MASK = 0x01 << NA_EnableFeatureClock_B,
	NTRX_UsePullup4Spiclk_MASK = 0x01 << NA_UsePullup4Spiclk_B,
	NTRX_UsePulldown4Spiclk_MASK = 0x01 << NA_UsePulldown4Spiclk_B,
	NTRX_UsePullup4Spissn_MASK = 0x01 << NA_UsePullup4Spissn_B,
	NTRX_UsePulldown4Spissn_MASK = 0x01 << NA_UsePulldown4Spissn_B,
	NTRX_UsePullup4Spirxd_MASK = 0x01 << NA_UsePullup4Spirxd_B,
	NTRX_UsePulldown4Spirxd_MASK = 0x01 << NA_UsePulldown4Spirxd_B,
	NTRX_UsePullup4Spitxd_MASK = 0x01 << NA_UsePullup4Spitxd_B,
	NTRX_UsePulldown4Spitxd_MASK = 0x01 << NA_UsePulldown4Spitxd_B,
	NTRX_UsePullup4Por_MASK = 0x01 << NA_UsePullup4Por_B,
	NTRX_UsePulldown4Por_MASK = 0x01 << NA_UsePulldown4Por_B,
	NTRX_UsePullup4Pamp_MASK = 0x01 << NA_UsePullup4Pamp_B,
	NTRX_UsePulldown4Pamp_MASK = 0x01 << NA_UsePulldown4Pamp_B,
	NTRX_UsePullup4Ucirq_MASK = 0x01 << NA_UsePullup4Ucirq_B,
	NTRX_UsePulldown4Ucirq_MASK = 0x01 << NA_UsePulldown4Ucirq_B,
	NTRX_UsePullup4Ucrst_MASK = 0x01 << NA_UsePullup4Ucrst_B,
	NTRX_UsePulldown4Ucrst_MASK = 0x01 << NA_UsePulldown4Ucrst_B,
	NTRX_WritePulls4Spi_MASK = 0x01 << NA_WritePulls4Spi_B,
	NTRX_WritePulls4Pads_MASK = 0x01 << NA_WritePulls4Pads_B,
	NTRX_TestModes_MASK = 0x0f << NA_TestModes_LSB,
	NTRX_RfTestSelect_MASK = 0x0f << NA_RfTestSelect_LSB,
	NTRX_RamIndex_MASK = 0x03 << NA_RamIndex_LSB,
	NTRX_DeviceSelect_MASK = 0x03 << NA_DeviceSelect_LSB,
	NTRX_TxIrqEnable_MASK = 0x01 << NA_TxIrqEnable_B,
	NTRX_RxIrqEnable_MASK = 0x01 << NA_RxIrqEnable_B,
	NTRX_BbTimerIrqEnable_MASK = 0x01 << NA_BbTimerIrqEnable_B,
	NTRX_LoIrqEnable_MASK = 0x01 << NA_LoIrqEnable_B,
	NTRX_TxIrqStatus_MASK = 0x01 << NA_TxIrqStatus_B,
	NTRX_RxIrqStatus_MASK = 0x01 << NA_RxIrqStatus_B,
	NTRX_BbTimerIrqStatus_MASK = 0x01 << NA_BbTimerIrqStatus_B,
	NTRX_LoIrqStatus_MASK = 0x01 << NA_LoIrqStatus_B,
	NTRX_TxIntsRawStat_MASK = 0x3f << NA_TxIntsRawStat_LSB,
	NTRX_TxIntsReset_MASK = 0x3f << NA_TxIntsReset_LSB,
	NTRX_RxIntsRawStat_MASK = 0x7f << NA_RxIntsRawStat_LSB,
	NTRX_RxIntsReset_MASK = 0x7f << NA_RxIntsReset_LSB,
	NTRX_LoIntsRawStat_MASK = 0x03 << NA_LoIntsRawStat_LSB,
	NTRX_LoIntsReset_MASK = 0x03 << NA_LoIntsReset_LSB,
	NTRX_ClearBasebandTimerInt_MASK = 0x01 << NA_ClearBasebandTimerInt_B,
	NTRX_TxIntsEn_MASK = 0x3f << NA_TxIntsEn_LSB,
	NTRX_RxIntsEn_MASK = 0x7f << NA_RxIntsEn_LSB,
	NTRX_LoIntsEn_MASK = 0x03 << NA_LoIntsEn_LSB,
	NTRX_LoEnableFastTuning_MASK = 0x01 << NA_LoEnableFastTuning_B,
	NTRX_LoFastTuningLevel_MASK = 0x07 << NA_LoFastTuningLevel_LSB,
	NTRX_LoEnableLsbNeg_MASK = 0x01 << NA_LoEnableLsbNeg_B,
	NTRX_LoEnableRecalib_MASK = 0x01 << NA_LoEnableRecalib_B,
	NTRX_UseLoRxCaps_MASK = 0x01 << NA_UseLoRxCaps_B,
	NTRX_LoTargetValue_MASK = 2,
	NTRX_AgcThresHold1_MASK = 0xff << NA_AgcThresHold1_LSB,
	NTRX_AgcThresHold2_MASK = 0xff << NA_AgcThresHold2_LSB,
	NTRX_HoldAgcInBitSync_MASK = 0x7f << NA_HoldAgcInBitSync_LSB,
	NTRX_HoldAgcInFrameSync_MASK = 0x01 << NA_HoldAgcInFrameSync_B,
	NTRX_AgcDeadTime_MASK = 0x3f << NA_AgcDeadTime_LSB,
	NTRX_AgcNregLength_MASK = 0x03 << NA_AgcNregLength_LSB,
	NTRX_AgcIntTime_MASK = 2,
	NTRX_AgcValue_MASK = 0x3f << NA_AgcValue_LSB,
	NTRX_AgcDefaultEn_MASK = 0x01 << NA_AgcDefaultEn_B,
	NTRX_AgcHold_MASK = 0x01 << NA_AgcHold_B,
	NTRX_AgcRssiThres_MASK = 0x3f << NA_AgcRssiThres_LSB,
	NTRX_AgcGain_MASK = 0x3f << NA_AgcGain_LSB,
	NTRX_AgcEnable_MASK = 0x01 << NA_AgcEnable_B,
	NTRX_ChirpFilterCaps_MASK = 0x0f << NA_ChirpFilterCaps_LSB,
	NTRX_FctClockEn_MASK = 0x01 << NA_FctClockEn_B,
	NTRX_StartFctMeasure_MASK = 0x01 << NA_StartFctMeasure_B,
	NTRX_EnableTx_MASK = 0x01 << NA_EnableTx_B,
	NTRX_FctPeriod_MASK = 0x0f << NA_FctPeriod_LSB,
	NTRX_ToaOffsetMeanDataValid_MASK = 0x01 << NA_ToaOffsetMeanDataValid_B,
	NTRX_PhaseOffsetData_MASK = 0x07 << NA_PhaseOffsetData_LSB,
	NTRX_PhaseOffsetAck_MASK = 0x07 << NA_PhaseOffsetAck_LSB,
	NTRX_ToaOffsetMeanAckValid_MASK = 0x01 << NA_ToaOffsetMeanAckValid_B,
	NTRX_RxPacketType_MASK = 0x0f << NA_RxPacketType_LSB,
	NTRX_RxAddrMatch_MASK = 0x0f << NA_RxAddrMatch_LSB,
	NTRX_RxCrc1Stat_MASK = 0x01 << NA_RxCrc1Stat_B,
	NTRX_RxCrc2Stat_MASK = 0x01 << NA_RxCrc2Stat_B,
	NTRX_RxCorrBitErr_MASK = 0x0f << NA_RxCorrBitErr_LSB,
	NTRX_RxCorrErrThres_MASK = 0x0f << NA_RxCorrErrThres_LSB,
	NTRX_RxAddrSegEsMatch_MASK = 0x01 << NA_RxAddrSegEsMatch_B,
	NTRX_RxAddrSegIsMatch_MASK = 0x01 << NA_RxAddrSegIsMatch_B,
	NTRX_RxCryptEn_MASK = 0x01 << NA_RxCryptEn_B,
	NTRX_RxCryptId_MASK = 0x03 << NA_RxCryptId_LSB,
	NTRX_RxCryptSeqN_MASK = 0x01 << NA_RxCryptSeqN_B,
	NTRX_TxTimeSlotControl_MASK = 0x01 << NA_TxTimeSlotControl_B,
	NTRX_RxTimeSlotControl_MASK = 0x01 << NA_RxTimeSlotControl_B,
	NTRX_TxArqCnt_MASK = 0x0f << NA_TxArqCnt_LSB,
	NTRX_TxArqMax_MASK = 0x0f << NA_TxArqMax_LSB,
	NTRX_CsqDitherValue_MASK = 0x03 << NA_CsqDitherValue_LSB,
	NTRX_CsqUsePhaseShift_MASK = 0x01 << NA_CsqUsePhaseShift_B,
	NTRX_CsqUse4Phases_MASK = 0x01 << NA_CsqUse4Phases_B,
	NTRX_CsqAsyMode_MASK = 0x01 << NA_CsqAsyMode_B,
	NTRX_CsqMemAddrInit_MASK = 0x01 << NA_CsqMemAddrInit_B,
	NTRX_CsqUseRam_MASK = 0x01 << NA_CsqUseRam_B,
	NTRX_CsqTest_MASK = 0x01 << NA_CsqTest_B,
	NTRX_CsqSetValue_MASK = 0x3f << NA_CsqSetValue_LSB,
	NTRX_CsqSetIValue_MASK = 0x01 << NA_CsqSetIValue_B,
	NTRX_CsqSetQValue_MASK = 0x01 << NA_CsqSetQValue_B,
	NTRX_D3lFixnMap_MASK = 0x01 << NA_D3lFixnMap_B,
	NTRX_D3lPomEn_MASK = 0x01 << NA_D3lPomEn_B,
	NTRX_D3lPomLen_MASK = 0x03 << NA_D3lPomLen_LSB,
	NTRX_D3lUpDownEx_MASK = 0x01 << NA_D3lUpDownEx_B,
	NTRX_LeaveMapThresh1InBitsync_MASK = 0x7f << NA_LeaveMapThresh1InBitsync_LSB,
	NTRX_UseMapThresh1InFramesync_MASK = 0x01 << NA_UseMapThresh1InFramesync_B,
	NTRX_Go2MapThresh1InBitsync_MASK = 0x7f << NA_Go2MapThresh1InBitsync_LSB,
	NTRX_D3lFixThres1MapEn_MASK = 0x01 << NA_D3lFixThres1MapEn_B,
	NTRX_EnableLO_MASK = 0x01 << NA_EnableLO_B,
	NTRX_EnableLOdiv10_MASK = 0x01 << NA_EnableLOdiv10_B,
	NTRX_EnableCsqClock_MASK = 0x01 << NA_EnableCsqClock_B,
	NTRX_InvertRxClock_MASK = 0x01 << NA_InvertRxClock_B,
	NTRX_EnableExtPA_MASK = 0x01 << NA_EnableExtPA_B,
	NTRX_EnableIntPA_MASK = 0x01 << NA_EnableIntPA_B,
	NTRX_EnableRxClock_MASK = 0x01 << NA_EnableRxClock_B,
	NTRX_EnableRx_MASK = 0x01 << NA_EnableRx_B,
	NTRX_LnaFreqAdjust_MASK = 0x7 << NA_LnaFreqAdjust_LSB,
	NTRX_TxPaBias_MASK = 0x7 << NA_TxPaBias_LSB,
	NTRX_TxOutputPower0_MASK = 0x3f << NA_TxOutputPower0_LSB,
	NTRX_TxOutputPower1_MASK = 0x3f << NA_TxOutputPower1_LSB,
	NTRX_RfRxCompValueI_MASK = 0x1f << NA_RfRxCompValueI_LSB,
	NTRX_RfRxCompValueQ_MASK = 0x1f << NA_RfRxCompValueQ_LSB,
	NTRX_SymbolDur_MASK = 0x7 << NA_SymbolDur_LSB,
	NTRX_SymbolRate_MASK = 0x7 << NA_SymbolRate_LSB,
	NTRX_ModulationSystem_MASK = 0x01 << NA_ModulationSystem_B,
	NTRX_Crc2Type_MASK = 0x3 << NA_Crc2Type_LSB,
	NTRX_UseFec_MASK = 0x01 << NA_UseFec_B,
	NTRX_TxRxCryptCrc2Mode_MASK = 0x01 << NA_TxRxCryptCrc2Mode_B,
	NTRX_TxRxCryptClkMode_MASK = 0x0f << NA_TxRxCryptClkMode_LSB,
	NTRX_SwapBbBuffers_MASK = 0x01 << NA_SwapBbBuffers_B,
	NTRX_TxRxBbBufferMode1_MASK = 0x01 << NA_TxRxBbBufferMode1_B,
	NTRX_TxRxBbBufferMode0_MASK = 0x01 << NA_TxRxBbBufferMode0_B,
	NTRX_FdmaEnable_MASK = 0x01 << NA_FdmaEnable_B,
	NTRX_TxRxMode_MASK = 0x01 << NA_TxRxMode_B,
	NTRX_ChirpMatrix0_MASK = 0x07 << NA_ChirpMatrix0_LSB,
	NTRX_ChirpMatrix1_MASK = 0x07 << NA_ChirpMatrix1_LSB,
	NTRX_ChirpMatrix2_MASK = 0x07 << NA_ChirpMatrix2_LSB,
	NTRX_ChirpMatrix3_MASK = 0x07 << NA_ChirpMatrix3_LSB,
	NTRX_TxPreTrailMatrix0_MASK = 0x03 << NA_TxPreTrailMatrix0_LSB,
	NTRX_TxPreTrailMatrix1_MASK = 0x03 << NA_TxPreTrailMatrix1_LSB,
	NTRX_TxUnderrunIgnore_MASK = 0x01 << NA_TxUnderrunIgnore_B,
	NTRX_TxMacCifsDis_MASK = 0x01 << NA_TxMacCifsDis_B,
	NTRX_TxVCarrSens_MASK = 0x01 << NA_TxVCarrSens_B,
	NTRX_TxPhCarrSenseMode_MASK = 0x03 << NA_TxPhCarrSenseMode_LSB,
	NTRX_TxVCarrSensAck_MASK = 0x01 << NA_TxVCarrSensAck_B,
	NTRX_TxArq_MASK = 0x01 << NA_TxArq_B,
	NTRX_Tx3Way_MASK = 0x01 << NA_Tx3Way_B,
	NTRX_TxBackOffAlg_MASK = 0x01 << NA_TxBackOffAlg_B,
	NTRX_TxFragPrio_MASK = 0x01 << NA_TxFragPrio_B,
	NTRX_TxBackOffSeed_MASK = 0xff << NA_TxBackOffSeed_LSB,
	NTRX_TxCryptSeqReset_MASK = 0x0f << NA_TxCryptSeqReset_LSB,
	NTRX_TxCryptEn_MASK = 0x01 << NA_TxCryptEn_B,
	NTRX_TxCryptId_MASK = 0x03 << NA_TxCryptId_LSB,
	NTRX_TxCryptSeqN_MASK = 0x01 << NA_TxCryptSeqN_B,
	NTRX_TxScrambInit_MASK = 0x7f << NA_TxScrambInit_LSB,
	NTRX_TxScrambEn_MASK = 0x01 << NA_TxScrambEn_B,
	NTRX_TxPacketType_MASK = 0x0f << NA_TxPacketType_LSB,
	NTRX_TxAddrSlct_MASK = 0x01 << NA_TxAddrSlct_B,
	NTRX_TxCmdStop_MASK = 0x01 << NA_TxCmdStop_B,
	NTRX_TxCmdStart_MASK = 0x01 << NA_TxCmdStart_B,
	NTRX_TxBufferCmd_MASK = 0x03 << NA_TxBufferCmd_LSB,
	NTRX_RxCmdStop_MASK = 0x01 << NA_RxCmdStop_B,
	NTRX_RxCmdStart_MASK = 0x01 << NA_RxCmdStart_B,
	NTRX_RxBufferCmd_MASK = 0x03 << NA_RxBufferCmd_LSB,
	NTRX_RxCryptSeqReset_MASK = 0x0f << NA_RxCryptSeqReset_LSB,
	NTRX_RxTimeBCrc1Mode_MASK = 0x01 << NA_RxTimeBCrc1Mode_B,
	NTRX_RxCrc2Mode_MASK = 0x01 << NA_RxCrc2Mode_B,
	NTRX_RxArqMode_MASK = 0x03 << NA_RxArqMode_LSB,
	NTRX_RxAddrSegEsMode_MASK = 0x01 << NA_RxAddrSegEsMode_B,
	NTRX_RxAddrSegIsMode_MASK = 0x01 << NA_RxAddrSegIsMode_B,
	NTRX_RxAddrSegDevIdL_MASK = 0x03 << NA_RxAddrSegDevIdL_LSB,
	NTRX_RxDataEn_MASK = 0x01 << NA_RxDataEn_B,
	NTRX_RxBrdcastEn_MASK = 0x01 << NA_RxBrdcastEn_B,
	NTRX_RxTimeBEn_MASK = 0x01 << NA_RxTimeBEn_B,
	NTRX_RxAddrMode_MASK = 0x01 << NA_RxAddrMode_B,
	NTRX_RangingPulses_MASK = 0x0f << NA_RangingPulses_LSB,
	NTRX_PulseDetDelay_MASK = 0x1f << NA_PulseDetDelay_LSB,
	NTRX_GateAdjThreshold_MASK = 0x07 << NA_GateAdjThreshold_LSB,
	NTRX_DownPulseDetectDis_MASK = 0x01 << NA_DownPulseDetectDis_B,
	NTRX_UpPulseDetectDis_MASK = 0x01 << NA_UpPulseDetectDis_B,
	NTRX_GateSizeUnsync_MASK = 0x03 << NA_GateSizeUnsync_LSB,
	NTRX_GateSizeBitsync_MASK = 0x03 << NA_GateSizeBitsync_LSB,
	NTRX_GateSizeFramesync_MASK = 0x03 << NA_GateSizeFramesync_LSB,
	NTRX_GateAdjBitsyncEn_MASK = 0x01 << NA_GateAdjBitsyncEn_B,
	NTRX_GateAdjFramesyncEn_MASK = 0x01 << NA_GateAdjFramesyncEn_B,
	NTRX_Go2BitsyncThreshold_MASK = 0x07 << NA_Go2BitsyncThreshold_LSB,
	NTRX_LeaveBitsyncThreshold_MASK = 0x07 << NA_LeaveBitsyncThreshold_LSB,
	NTRX_RtcTimeBTxAdj_MASK = 0xff << NA_RtcTimeBTxAdj_LSB,
	NTRX_RtcTimeBRxAdj_MASK = 0xff << NA_RtcTimeBRxAdj_LSB,
	NTRX_RtcCmdWr_MASK = 0x01 << NA_RtcCmdWr_B,
	NTRX_RtcCmdRd_MASK = 0x01 << NA_RtcCmdRd_B,
	NTRX_RtcTimeBAutoMode_MASK = 0x01 << NA_RtcTimeBAutoMode_B,
	NTRX_RtcTimeBTestMode_MASK = 0x01 << NA_RtcTimeBTestMode_B,
	NTRX_AgcAmplitude_MASK = 0xff << NA_AgcAmplitude_LSB,
	NTRX_AgcRangeOffset_MASK = 0xff << NA_AgcRangeOffset_LSB,
	NTRX_UseAlternativeAgc_MASK = 0x01 << NA_UseAlternativeAgc_B,
	NTRX_TxRxDigTestMode_MASK = 0x01 << NA_TxRxDigTestMode_B,
	NTRX_DebugMacRxCmd_MASK = 0x01 << NA_DebugMacRxCmd_B,
	NTRX_DebugMacTxCmd_MASK = 0x01 << NA_DebugMacTxCmd_B,
	NTRX_BistBbRamReset_MASK = 0x01 << NA_BistBbRamReset_B,
	NTRX_BistBbRamActive_MASK = 0x01 << NA_BistBbRamActive_B,
	NTRX_BistCsqRamReset_MASK = 0x01 << NA_BistCsqRamReset_B,
	NTRX_BistCsqRamActive_MASK = 0x01 << NA_BistCsqRamActive_B,
	NTRX_DebugMacFsm_MASK = 0x0f << NA_DebugMacFsm_LSB,
	NTRX_DebugMacTxRxCtrl_MASK = 0x0f << NA_DebugMacTxRxCtrl_LSB,
	NTRX_DebugBitProcFsm_MASK = 0x0f << NA_DebugBitProcFsm_LSB,
	NTRX_DebugBitProcTx_MASK = 0x01 << NA_DebugBitProcTx_B,
	NTRX_DebugBitProcRx_MASK = 0x01 << NA_DebugBitProcRx_B,
	NTRX_DebugRxDetStatus_MASK = 0x03 << NA_DebugRxDetStatus_LSB,
	NTRX_RamTxLength_MASK = 2,
	NTRX_RamStaAddr0_MASK = 6,
	NTRX_SyncWord_MASK = 6,
	NTRX_ToaOffsetMeanData_MASK = 2,
	NTRX_TxRespTime_MASK = 2,
	NTRX_ToaOffsetMeanAck_MASK = 2
} TRX_REG_MASK;

static uint8_t TRXShadowReg[] =
{
  0,   0,   0,   0,   0,   0,   0,   6,
  0,   0,   0,   0,   0,   0,   0,   0,
  0,   0,   0,   0,   0,   0,   0,   0,
  0,   0,   0,   0,   0,   0,   0,   3,
  6, 152,  12,   0,   0,  63,  30,   6,
  0,   0, 171, 105, 202, 148, 146, 213,
 44, 171,  48,   0,   0,   0,   0,   0,
  0,   0,   0,   0, 224,   4,   0,   1,
  3,   7,   0,   3,  63,  63,  15,  15,
115,   0,  16,  16,  67,  20,  16,   0,
  0, 255,   0,   0,   0,   0,   0,   0,
  0,   0,  11,  95,   5,   7, 213,  98,
  0,   0,   0,  12,  10,   0,   0,   0,
  0,   0,   0,   0,   0,   0,   0,   0,
  0,   0,   0,   0,   0,   0,   0,   0,
  0,   0,   0,   0,   0,  80,   0,   0
};


// 16
static uint8_t NA5TR1_Rx_80MHz[] =
{
	0x02, 0x63, 0x39, 0xC7, 0x0E, 0x0F, 0xC0, 0x1F, 0xFF, 0xE0, 0x0F, 0xC3, 0xC3, 0x8E, 0x73, 0x39, 
	0x00, 0xCE, 0x63, 0x1C, 0x38, 0x3E, 0x03, 0xFF, 0xFF, 0xFF, 0x01, 0xF0, 0xF0, 0xE7, 0x19, 0x8C
};


// 4
static uint8_t NA5TR1_Rx_22MHz[] =
{
	0xC6, 0x0F, 0xF0, 0x63, 
	0x9C, 0x7F, 0xFE, 0x39
};


// 61
static uint8_t NA5TR1_Tx_80MHz[] =
{
	0x20, 0xE0, 0x1D, 0xDE, 0x27, 0xA3, 0x12, 0x17, 0xF1, 0xB1, 0x10, 0x04, 0xA4, 0xFF, 0x6D, 0x09, 
	0x03, 0xE2, 0xBD, 0x75, 0xD4, 0xC0, 0x0D, 0x2C, 0x7F, 0x35, 0x19, 0x03, 0xC3, 0x57, 0xB1, 0xBF, 
	0x39, 0xA5, 0xCF, 0x02, 0xC2, 0x0F, 0xE2, 0x73, 0xFD, 0xFE, 0x77, 0xEA, 0x5B, 0x4F, 0x85, 0x01, 
	0x80, 0x84, 0x49, 0x10, 0xD7, 0x9E, 0xE4, 0x2A, 0xEE, 0xB1, 0x33, 0x75, 0x75, 
	0x08, 0xF7, 0xF7, 0x48, 0x1A, 0x56, 0xA4, 0x09, 0xCD, 0xE8, 0x81, 0xA4, 0xED, 0x4E, 0x36, 0xA0, 
	0xE4, 0xFC, 0x9F, 0x89, 0x21, 0xC0, 0x97, 0xDE, 0x5F, 0x9A, 0x13, 0x20, 0xD2, 0xE9, 0xAE, 0x5F, 
	0xDC, 0x16, 0x51, 0x60, 0xB1, 0xA6, 0xFA, 0x8E, 0x9F, 0x9E, 0xAC, 0x28, 0x05, 0x52, 0xE0, 0x90, 
	0x40, 0xE1, 0x63, 0xB5, 0xE6, 0xF8, 0xF9, 0xDB, 0xCB, 0xAC, 0x8D, 0x7D, 0x6D, 
	0x7E, 0x79, 0x85, 0x96, 0x6E, 0x51, 0x95, 0xCF, 0x7A, 0x14, 0x5C, 0xEA, 0xDB, 0x42, 0x04, 0x6C, 
	0xEE, 0xE3, 0x62, 0x04, 0x30, 0xB1, 0xFF, 0xCF, 0x56, 0x04, 0x1C, 0x7D, 0xE2, 0xFF, 0xC7, 0x62, 
	0x14, 0x04, 0x30, 0x81, 0xD2, 0xFB, 0xF7, 0xC7, 0x86, 0x45, 0x14, 0x00, 0x08, 0x24, 0x4C, 0x7D, 
	0xA6, 0xCA, 0xE7, 0xF7, 0xFF, 0xFF, 0xFB, 0xF7, 0xEF, 0xE7, 0xE3, 0xDF, 0xDB
};


// 8
static uint8_t NA5TR1_Tx_22MHz[] =
{
	0x22, 0x54, 0x1E, 0xB9, 0x07, 0xC8, 0xA4, 0xB3, 
	0x5C, 0x40, 0xFF, 0xC7, 0xC0, 0x55, 0xFB, 0x8D, 
	0x5E, 0x9C, 0xB7, 0x00, 0x8C, 0xFB, 0xF3, 0xDB
};


#define TxEND (0x01 << NA_TxEnd_B)
#define TX_IRQ_MASK TxEND

#define NTRX_TX_START (0x01 << NA_TxCmdStart_B)
#define NTRX_TX_BUFF0 (0x01 << NA_TxBufferCmd_LSB)
#define NTRX_TX_BUFF1 (0x01 << NA_TxBufferCmd_MSB)


#endif /* RF_NTRX_H */