rf_ntrx.h

6lowPan的协议栈

#define NA_DebugBitProcTx_B                           (4)
#define NA_DebugBitProcRx_B                           (5)
#define NA_DebugRxDetStatus_LSB                       (6)
#define NA_RamStaAddr0_LSB                            (0)
#define NA_RamStaAddr1_LSB                            (0)
#define NA_RamTxDstAddr_LSB                           (0)
#define NA_RamTxLength_LSB                            (0)
#define NA_RamTxFragC_B                               (5)
#define NA_RamTxSeqN_B                                (6)
#define NA_RamTxLCh_B                                 (7)
#define NA_RamRxDstAddr_LSB                           (0)
#define NA_RamRxSrcAddr_LSB                           (0)
#define NA_RamRxLength_LSB                            (0)
#define NA_RamRxFragC_B                               (5)
#define NA_RamRxSeqN_B                                (6)
#define NA_RamRxLCh_B                                 (7)
#define NA_RamRtcTx_LSB                               (0)
#define NA_RamRtcRx_LSB                               (0)
#define NA_RamRtcReg_LSB                              (0)
#define NA_RamTxRxCryptKey_LSB                        (0)
#define NA_RamTxCryptClock_LSB                        (0)
#define NA_RamRxCryptClock_LSB                        (0)
#define NA_RamRxBuffer_LSB                            (0)
#define NA_RamTxBuffer_LSB                            (0)
#define NA_RamTxRxBuffer_LSB                          (0)
#define NA_RamRxTransBuffer_LSB                       (0)
#define NA_RamTxTransBuffer_LSB                       (0)
#define NA_RamTxRxTransBuffer_LSB                     (0)
#define NA_RamCsqDataByte0_LSB                        (0)
#define NA_RamCsqDataByte1_LSB                        (0)
#define NA_RamCsqDataByte2_LSB                        (0)
#define NA_RamD3lPatI_O                               (0x80)
#define NA_RamD3lPatI_LSB                             (0)
#define NA_RamD3lPatQ_O                               (0x180)
#define NA_RamD3lPatQ_LSB                             (0)
#define NA_RamD3lThresDown_LSB                        (0)
#define NA_RamD3lThresUp_LSB                          (0)
#define NA_TxRxPacketLength_LSB                       (0)
#define NA_IrqPolarity_B                              (2)
#define NA_IrqDriver_B                                (3)
#define NA_ClearBasebandTimerInt_B                    (7)
#define NA_ClearBasebandTimerInt_B                    (7)
#define NA_ChirpFilterCaps_LSB                        (0)
#define NA_CsqDitherValue_LSB                         (0)
#define NA_CsqUse4Phases_B                            (3)
#define NA_CsqAsyMode_B                               (4)
#define NA_CsqTest_B                                  (7)
#define NA_CsqSetValue_LSB                            (0)
#define NA_CsqSetIValue_B                             (6)
#define NA_CsqSetQValue_B                             (7)
#define NA_InvertRxClock_B                            (3)
#define NA_Crc2Type_LSB                               (0)
#define NA_ChirpMatrix0_LSB                           (0)
#define NA_ChirpMatrix1_LSB                           (4)
#define NA_ChirpMatrix2_LSB                           (0)
#define NA_ChirpMatrix3_LSB                           (4)
#define NA_RamTxBuffer_O                              (0x380)
#define NA_RamTxLength_O                              (0x98)
#define NA_RamTxDstAddr_O                             (0x90)
#define NA_TxBufferCmd_O                              (0x55)
#define NA_TxBufferCmd_MSB                            (3)
#define NA_RxCrc2Stat_O                               (0x31)
#define NA_RamRxDstAddr_O                             (0xA8)
#define NA_RamRxSrcAddr_O                             (0xB0)
#define NA_RamRxLength_O                              (0xB8)
#define NA_RamRxBuffer_O                              (0x280)
#define NA_RxCmdStart_O                               (0x56)
#define NA_RxBufferCmd_MSB                            (3)





typedef enum
{
// 0x00 = 0x,
	TRX_REG_SpiBitOrder = 0x00,
	TRX_REG_SpiTxDriver = 0x00,
	TRX_REG_IrqPolarity = 0x00,
	TRX_REG_IrqDriver = 0x00,
//0x01 = 0x,
	TRX_REG_WakeUpTimeByte = 0x01,
//0x02 = 0x,
	TRX_REG_WakeUpTimeWe = 0x02,
//0x03 = 0x,
	TRX_REG_BattMgmtEnable = 0x03,
	TRX_REG_BattMgmtThreshold = 0x03,
	TRX_REG_BattMgmtCompare = 0x03,
//0x04 = 0x,
	TRX_REG_DioDirection = 0x04,
	TRX_REG_DioOutValueAlarmEnable = 0x04,
	TRX_REG_DioAlarmStart = 0x04,
	TRX_REG_DioAlarmPolarity = 0x04,
	TRX_REG_DioUsePullup = 0x04,
	TRX_REG_DioUsePulldown = 0x04,
//0x05 = 0x,
	TRX_REG_DioPortWe = 0x05,
//0x06 = 0x,
	TRX_REG_EnableWakeUpRtc = 0x06,
	TRX_REG_EnableWakeUpDio = 0x06,
	TRX_REG_PowerUpTime = 0x06,
	TRX_REG_PowerDownMode = 0x06,
//0x07 = 0x,
	TRX_REG_PowerDown = 0x07,
	TRX_REG_ResetBbClockGate = 0x07,
	TRX_REG_ResetBbRadioCtrl = 0x07,
//0x08 = 0x,
	TRX_REG_EnableBbCrystal = 0x08,
	TRX_REG_EnableBbClock = 0x08,
	TRX_REG_BypassBbCrystal = 0x08,
	TRX_REG_FeatureClockFreq = 0x08,
	TRX_REG_EnableFeatureClock = 0x08,
//0x09 = 0x,
	TRX_REG_UsePullup4Spiclk = 0x09,
	TRX_REG_UsePulldown4Spiclk = 0x09,
	TRX_REG_UsePullup4Spissn = 0x09,
	TRX_REG_UsePulldown4Spissn = 0x09,
	TRX_REG_UsePullup4Spirxd = 0x09,
	TRX_REG_UsePulldown4Spirxd = 0x09,
	TRX_REG_UsePullup4Spitxd = 0x09,
	TRX_REG_UsePulldown4Spitxd = 0x09,
//0x0a = 0x,
	TRX_REG_UsePullup4Por = 0xa,
	TRX_REG_UsePulldown4Por = 0xa,
	TRX_REG_UsePullup4Pamp = 0xa,
	TRX_REG_UsePulldown4Pamp = 0xa,
	TRX_REG_UsePullup4Ucirq = 0xa,
	TRX_REG_UsePulldown4Ucirq = 0xa,
	TRX_REG_UsePullup4Ucrst = 0xa,
	TRX_REG_UsePulldown4Ucrst = 0xa,
//0x0b = 0x,
	TRX_REG_WritePulls4Spi = 0xb,
	TRX_REG_WritePulls4Pads = 0xb,
//0x0c = 0x,
	TRX_REG_TestModes = 0xc,
//0x0d = 0x,
	TRX_REG_RfTestSelect = 0xd,
//0x0e = 0x,
	TRX_REG_RamIndex = 0xe,
	TRX_REG_DeviceSelect = 0xe,
//0x0f = 0x,
	TRX_REG_TxIrqEnable = 0xf,
	TRX_REG_RxIrqEnable = 0xf,
	TRX_REG_BbTimerIrqEnable = 0xf,
	TRX_REG_LoIrqEnable = 0xf,
//0x10 = 0x,
	TRX_REG_TxIntsReset = 0x10,
//0x11 = 0x,
	TRX_REG_RxIntsReset = 0x11,
//0x12 = 0x,
	TRX_REG_LoIntsReset = 0x12,
	TRX_REG_ClearBasebandTimerInt = 0x12,
//0x13 = 0x,
	TRX_REG_TxIntsEn = 0x13,
//0x14 = 0x,
	TRX_REG_RxIntsEn = 0x14,
//0x15 = 0x,
	TRX_REG_LoIntsEn = 0x15,
//0x1c = 0x,
	TRX_REG_LoEnableFastTuning = 0x1c,
	TRX_REG_LoFastTuningLevel = 0x1c,
	TRX_REG_LoEnableLsbNeg = 0x1c,
	TRX_REG_LoEnableRecalib = 0x1c,
	TRX_REG_UseLoRxCaps = 0x1c,
//0x1d = 0x,
	TRX_REG_LoTargetValue = 0x1d,
//0x1f = 0x,
	TRX_REG_AgcThresHold1 = 0x1f,
//0x20 = 0x,
	TRX_REG_AgcThresHold2 = 0x20,
//0x21 = 0x,
	TRX_REG_HoldAgcInBitSync = 0x21,
	TRX_REG_HoldAgcInFrameSync = 0x21,
//0x22 = 0x,
	TRX_REG_AgcDeadTime = 0x22,
	TRX_REG_AgcNregLength = 0x22,
//0x23 = 0x,
	TRX_REG_AgcIntTime = 0x23,
//0x25 = 0x25,
	TRX_REG_AgcValue = 0x25,
	TRX_REG_AgcDefaultEn = 0x25,
	TRX_REG_AgcHold = 0x25,
//0x26 = 0x,
	TRX_REG_AgcRssiThres = 0x26,
	TRX_REG_AgcEnable = 0x26,
//0x27 = 0x,
	TRX_REG_ChirpFilterCaps = 0x27,
	TRX_REG_FctClockEn = 0x27,
	TRX_REG_StartFctMeasure = 0x27,
	TRX_REG_EnableTx = 0x27,
	TRX_REG_FctPeriod = 0x27,
//0x2b	 = 0x,
//0x2e = 0x,
//0x30 = 0x,
//0x31 = 0x,
//0x32 = 0x,
//0x33 = 0x,
//0x37 = 0x,
	TRX_REG_TxTimeSlotControl = 0x37,
//0x3c = 0x,
	TRX_REG_TxArqMax = 0x3c,
//0x3d = 0x,
	TRX_REG_CsqDitherValue = 0x3d,
	TRX_REG_CsqUsePhaseShift = 0x3d,
	TRX_REG_CsqUse4Phases = 0x3d,
	TRX_REG_CsqAsyMode = 0x3d,
	TRX_REG_CsqMemAddrInit = 0x3d,
	TRX_REG_CsqUseRam = 0x3d,
	TRX_REG_CsqTest = 0x3d,
//0x3e = 0x,
	TRX_REG_CsqSetValue = 0x3e,
	TRX_REG_CsqSetIValue = 0x3e,
	TRX_REG_CsqSetQValue = 0x3e,
//0x3f = 0x,
	TRX_REG_D3lFixnMap = 0x3f,
	TRX_REG_D3lPomEn = 0x3f,
	TRX_REG_D3lPomLen = 0x3f,
	TRX_REG_D3lUpDownEx = 0x3f,
//0x40 = 0x,
	TRX_REG_LeaveMapThresh1InBitsync = 0x40,
	TRX_REG_UseMapThresh1InFramesync = 0x40,
//0x41 = 0x,
	TRX_REG_Go2MapThresh1InBitsync = 0x41,
	TRX_REG_D3lFixThres1MapEn = 0x41,
//0x42 = 0x,
	TRX_REG_EnableLO = 0x42,
	TRX_REG_EnableLOdiv10 = 0x42,
	TRX_REG_EnableCsqClock = 0x42,
	TRX_REG_InvertRxClock = 0x42,
	TRX_REG_EnableExtPA = 0x42,
	TRX_REG_EnableIntPA = 0x42,
	TRX_REG_EnableRxClock = 0x42,
	TRX_REG_EnableRx = 0x42,
//0x43 = 0x,
	TRX_REG_LnaFreqAdjust = 0x43,
	TRX_REG_TxPaBias = 0x43,
//0x44 = 0x,
	TRX_REG_TxOutputPower0 = 0x44,
//0x45 = 0x,
	TRX_REG_TxOutputPower1 = 0x45,
//0x46 = 0x,
	TRX_REG_RfRxCompValueI = 0x46,
//0x47 = 0x,
	TRX_REG_RfRxCompValueQ = 0x47,
//0x48 = 0x,
	TRX_REG_SymbolDur = 0x48,
	TRX_REG_SymbolRate = 0x48,
	TRX_REG_ModulationSystem = 0x48,
//0x49 = 0x,
	TRX_REG_Crc2Type = 0x49,
	TRX_REG_UseFec = 0x49,
	TRX_REG_TxRxCryptCrc2Mode = 0x49,
	TRX_REG_TxRxCryptClkMode = 0x49,
//0x4a = 0x,
	TRX_REG_SwapBbBuffers = 0x4a,
	TRX_REG_TxRxBbBufferMode1 = 0x4a,
	TRX_REG_TxRxBbBufferMode0 = 0x4a,
	TRX_REG_FdmaEnable = 0x4a,
	TRX_REG_TxRxMode = 0x4a,
//0x4b = 0x,
	TRX_REG_ChirpMatrix0 = 0x4b,
	TRX_REG_ChirpMatrix1 = 0x4b,
//0x4c = 0x,
	TRX_REG_ChirpMatrix2 = 0x4c,
	TRX_REG_ChirpMatrix3 = 0x4c,
//0x4d = 0x,
	TRX_REG_TxPreTrailMatrix0 = 0x4d,
	TRX_REG_TxPreTrailMatrix1 = 0x4d,
	TRX_REG_TxUnderrunIgnore = 0x4d,
	TRX_REG_TxMacCifsDis = 0x4d,
//0x4e = 0x,
	TRX_REG_TxVCarrSens = 0x4e,
	TRX_REG_TxPhCarrSenseMode = 0x4e,
	TRX_REG_TxVCarrSensAck = 0x4e,
	TRX_REG_TxArq = 0x4e,
	TRX_REG_Tx3Way = 0x4e,
	TRX_REG_TxBackOffAlg = 0x4e,
	TRX_REG_TxFragPrio = 0x4e,
//0x4f = 0x,
	TRX_REG_TxBackOffSeed = 0x4f,
//0x50 = 0x,
	TRX_REG_TxCryptSeqReset = 0x50,
	TRX_REG_TxCryptEn = 0x50,
	TRX_REG_TxCryptId = 0x50,
	TRX_REG_TxCryptSeqN = 0x50,
//0x51 = 0x,
	TRX_REG_TxScrambInit = 0x51,
	TRX_REG_TxScrambEn = 0x51,
//0x54 = 0x,
	TRX_REG_TxPacketType = 0x54,
	TRX_REG_TxAddrSlct = 0x54,
//0x55 = 0x,
	TRX_REG_TxCmdStop = 0x55,
	TRX_REG_TxCmdStart = 0x55,
	TRX_REG_TxBufferCmd = 0x55,
//0x56 = 0x,
	TRX_REG_RxCmdStop = 0x56,
	TRX_REG_RxCmdStart = 0x56,
	TRX_REG_RxBufferCmd = 0x56,
//0x57 = 0x,
	TRX_REG_RxCryptSeqReset = 0x57,
//0x5a = 0x,
	TRX_REG_RxTimeBCrc1Mode = 0x5a,
	TRX_REG_RxCrc2Mode = 0x5a,
	TRX_REG_RxArqMode = 0x5a,
	TRX_REG_RxAddrSegEsMode = 0x5a,
	TRX_REG_RxAddrSegIsMode = 0x5a,
	TRX_REG_RxAddrSegDevIdL = 0x5a,
//0x5b = 0x,
	TRX_REG_RxDataEn = 0x5b,
	TRX_REG_RxBrdcastEn = 0x5b,
	TRX_REG_RxTimeBEn = 0x5b,
	TRX_REG_RxAddrMode = 0x5b,
	TRX_REG_RangingPulses = 0x5b,
//0x5c = 0x,
	TRX_REG_PulseDetDelay = 0x5c,
//0x5d = 0x,
	TRX_REG_GateAdjThreshold = 0x5d,
	TRX_REG_DownPulseDetectDis = 0x5d,
	TRX_REG_UpPulseDetectDis = 0x5d,
//0x5e = 0x,
	TRX_REG_GateSizeUnsync = 0x5e,
	TRX_REG_GateSizeBitsync = 0x5e,
	TRX_REG_GateSizeFramesync = 0x5e,
	TRX_REG_GateAdjBitsyncEn = 0x5e,
	TRX_REG_GateAdjFramesyncEn = 0x5e,
//0x5f = 0x,
	TRX_REG_Go2BitsyncThreshold = 0x5f,
	TRX_REG_LeaveBitsyncThreshold = 0x5f,
//0x60 = 0x,
	TRX_REG_RtcTimeBTxAdj = 0x60,
//0x61 = 0x,
	TRX_REG_RtcTimeBRxAdj = 0x61,
//0x62 = 0x,
	TRX_REG_RtcCmdWr = 0x62,
	TRX_REG_RtcCmdRd = 0x62,
	TRX_REG_RtcTimeBAutoMode = 0x62,
	TRX_REG_RtcTimeBTestMode = 0x62,
//0x63 = 0x,
	TRX_REG_AgcAmplitude = 0x63,
//0x64 = 0x,
	TRX_REG_AgcRangeOffset = 0x64,
	TRX_REG_UseAlternativeAgc = 0x64,
//0x7d = 0x,
	TRX_REG_TxRxDigTestMode = 0x7d,
	TRX_REG_BistBbRamReset = 0x7d,
	TRX_REG_BistBbRamActive = 0x7d,
	TRX_REG_BistCsqRamReset = 0x7d,
	TRX_REG_BistCsqRamActive = 0x7d,
//0x7e = 0x,
//0x7f = 0x,
	TRX_REG_RamTxLength = 0x7f,
	TRX_REG_RamStaAddr0 = 0x7f,
	TRX_REG_SyncWord = 0x7f,
} TRX_W_REG;

typedef enum{