w90p710_lcd.h

winbond w90p710 lcd frame buffer driver。

             LCD_LCDCON_YUVSEQ;             /* YUV output sequence */
typedef enum {LCD_LCDCON_RGBSEQ_RGB = 0x00000000,
              LCD_LCDCON_RGBSEQ_BGR = 0x00000400, 
              LCD_LCDCON_RGBSEQ_GBR = 0x00000800,              
              LCD_LCDCON_RGBSEQ_RBG = 0x00000C00} 
             LCD_LCDCON_RGBSEQ;             /* LCD Line Data Sequence */
typedef enum {LCD_LCDCON_LCDBUS_24 = 0x00000000,
              LCD_LCDCON_LCDBUS_18 = 0x00000100, 
              LCD_LCDCON_LCDBUS_08 = 0x00000200} 
             LCD_LCDCON_LCDBUS;                /* Video Data output re-map */
#define LCD_LCDCON_OSDLUTEN  0x00000080     /* (NEW) */
typedef enum {LCD_LCDCON_OSDBPP_01 = 0x00000000,
 			  LCD_LCDCON_OSDBPP_02 = 0x00000010, 
 			  LCD_LCDCON_OSDBPP_04 = 0x00000020, 
 			  LCD_LCDCON_OSDBPP_08 = 0x00000030,
              LCD_LCDCON_OSDBPP_12 = 0x00000040, 
              LCD_LCDCON_OSDBPP_16 = 0x00000050, 
              LCD_LCDCON_OSDBPP_18 = 0x00000060, 
              LCD_LCDCON_OSDBPP_24 = 0x00000070} 
             LCD_LCDCON_OSDBPP;             /* (NEW) */
#define LCD_LCDCON_VDLUTEN   0x00000008     /* (NEW) */
typedef enum {LCD_LCDCON_BPP_01, LCD_LCDCON_BPP_02, LCD_LCDCON_BPP_04, LCD_LCDCON_BPP_08,
              LCD_LCDCON_BPP_12, LCD_LCDCON_BPP_16, LCD_LCDCON_BPP_18, LCD_LCDCON_BPP_24} 
             LCD_LCDCON_BPP;                /* LCD bits per pixel */

#define LCD_LCDINTENB_UNDREN2  0x00040000   /* FIFO2 UNDERRUN interrupt enable */
#define LCD_LCDINTENB_UNDREN1  0x00020000   /* FIFO1 UNDERRUN interrupt enable */
#define LCD_LCDINTENB_AHBEREN  0x00010000   /* AHB ERROR interrupt enable */
#define LCD_LCDINTENB_HSEN     0x00000020   /* HSYNC interrupt enable */
#define LCD_LCDINTENB_VSEN     0x00000010   /* VSYNC interrupt enable */
#define LCD_LCDINTENB_VLFINEN2 0x00000008   /* FIFO2 VLINE FINISH interrupt enable */
#define LCD_LCDINTENB_VFFINEN2 0x00000004   /* FIFO2 VFRAME FINISH interrupt enable */
#define LCD_LCDINTENB_VLFINEN1 0x00000002   /* FIFO1 VLINE FINISH interrupt enable */
#define LCD_LCDINTENB_VFFINEN1 0x00000001   /* FIFO1 VFRAME FINISH interrupt enable */

#define LCD_LCDINTS_UNDRIS2    0x00040000   /* FIFO2 have no data for output to Panel */
#define LCD_LCDINTS_UNDRIS1    0x00020000   /* FIFO1 have no data for output to Panel */
#define LCD_LCDINTS_AHBERIS    0x00010000   /* AHB master bus error status */
#define LCD_LCDINTS_HSIS       0x00000020   /* Timing Generator output a HSYNC pulse */
#define LCD_LCDINTS_VSIS       0x00000010   /* Timing Generator output a VSYNC pulse */
#define LCD_LCDINTS_VLFINIS2   0x00000008   /* FIFO2 transfer one line stream complete */
#define LCD_LCDINTS_VFFINIS2   0x00000004   /* FIFO2 transfer one frame stream complete */
#define LCD_LCDINTS_VLFINIS1   0x00000002   /* FIFO1 transfer one line stream complete */
#define LCD_LCDINTS_VFFINIS1   0x00000001   /* FIFO1 transfer one frame stream complete */
                               
#define LCD_LCDINTC_UNDRIC2    0x00040000   /* Clear FIFO2 UNDERRUN interrupt */
#define LCD_LCDINTC_UNDRIC1    0x00020000   /* Clear FIFO1 UNDERRUN interrupt */
#define LCD_LCDINTC_AHBERIC    0x00010000   /* Clear MBERROR interrupt */
#define LCD_LCDINTC_HSIC       0x00000020   /* Clear HSYNC interrupt */
#define LCD_LCDINTC_VSIC       0x00000010   /* Clear VSYNC interrupt */
#define LCD_LCDINTC_VLFINIC2   0x00000008   /* Clear FIFO2 VLINEFINSH interrupt */
#define LCD_LCDINTC_VFFINIC2   0x00000004   /* Clear FIFO2 VFRAMFINSH interrupt */
#define LCD_LCDINTC_VLFINIC1   0x00000002   /* Clear FIFO1 VLINEFINSH interrupt */
#define LCD_LCDINTC_VFFINIC1   0x00000001   /* Clear FIFO1 VFRAMFINSH interrupt */

typedef enum {LCD_OSDUPSCF_OSDHUP_1X = 0x00000000, 
              LCD_OSDUPSCF_OSDHUP_2X = 0x00000008, 
              LCD_OSDUPSCF_OSDHUP_4X = 0x00000010} 
             LCD_OSDUPSCF_OSDHUP;           /* OSD Stream Horizontal Up-scaling */
typedef enum {LCD_OSDUPSCF_OSDVUP_1X = 0x00000000, 
              LCD_OSDUPSCF_OSDVUP_2X = 0x00000002, 
              LCD_OSDUPSCF_OSDVUP_4X = 0x00000004} 
             LCD_OSDUPSCF_OSDVUP;           /* OSD Stream Vertical Up-scaling */             

typedef enum {LCD_VDUPSCF_VDHUP_1X = 0x00000000, 
              LCD_VDUPSCF_VDHUP_2X = 0x00000008, 
              LCD_VDUPSCF_VDHUP_4X = 0x00000010} 
             LCD_VDUPSCF_VDHUP;             /* Video Horizontal Up-scaling control */
typedef enum {LCD_VDUPSCF_VDVUP_1X = 0x00000000, 
              LCD_VDUPSCF_VDVUP_2X = 0x00000002, 
              LCD_VDUPSCF_VDVUP_4X = 0x00000004} 
             LCD_VDUPSCF_VDVUP;             /* Video Vertical Up-scaling control */        

#define LCD_FIFOCON_BPP24SW    0x00080000   /* FIFO 24bpp image swap control bit */
#define LCD_FIFOCON_BPP18SW    0x00040000   /* FIFO 18bpp image swap control bit */
#define LCD_FIFOCON_HSWP       0x00020000   /* FIFO half-word swap control bit */
#define LCD_FIFOCON_BSWP       0x00010000   /* FIFO byte swap control bit */
typedef enum {LCD_FIFOCON_FIFOEN_FIFO1 = 0x00000001, 
              LCD_FIFOCON_FIFOEN_FIFO2 = 0x00000002} 
             LCD_FIFOCON_FIFOEN;            /* FIFOs transfer data enable */     
             
typedef enum {LCD_FIFOSTATUS_MASTERID_FIFO1 = 0x00000001, 
              LCD_FIFOSTATUS_MASTERID_FIFO2 = 0x00000002} 
             LCD_FIFOSTATUS_MASTERID;       /* Currently, the data bus master */             
             
#define LCD_FIFO1PRM_F1LOCK    0x00000010   /* FIFO1 lock transfer enable */   
typedef enum {LCD_FIFO1PRM_F1BURSTY_04DATABURST = 0x00000000, 
              LCD_FIFO1PRM_F1BURSTY_08DATABURST = 0x00000004, 
              LCD_FIFO1PRM_F1BURSTY_16DATABURST = 0x00000008} 
             LCD_FIFO1PRM_F1BURSTY;         /* FIFO1 burst transfer type */  
typedef enum {LCD_FIFO1PRM_F1TRANSZ_1BYTE, 
              LCD_FIFO1PRM_F1TRANSZ_2BYTE, 
              LCD_FIFO1PRM_F1TRANSZ_4BYTE} 
             LCD_FIFO1PRM_F1TRANSZ;         /* FIFO1 data width per-transfer */               

#define LCD_FIFO2PRM_F2LOCK    0x00000010   /* FIFO2 lock transfer enable */   
typedef enum {LCD_FIFO2PRM_F2BURSTY_04DATABURST = 0x00000000,  
              LCD_FIFO2PRM_F2BURSTY_08DATABURST = 0x00000004, 
              LCD_FIFO2PRM_F2BURSTY_16DATABURST = 0x00000008} 
             LCD_FIFO2PRM_F2BURSTY;         /* FIFO2 burst transfer type */  
typedef enum {LCD_FIFO2PRM_F2TRANSZ_1BYTE, 
              LCD_FIFO2PRM_F2TRANSZ_2BYTE, 
              LCD_FIFO2PRM_F2TRANSZ_4BYTE} 
             LCD_FIFO2PRM_F2TRANSZ;         /* FIFO2 data width per-transfer */        
             
#define LCD_OSDOVCN_OSDBLI    0x00000200    /* OSD Blinking Control */  
#define LCD_OSDOVCN_OSDCKY    0x00000100    /* OSD Color Key Control */  
typedef enum {LCD_OSDOVCN_OCR1_VIDEO = 0x00000000, 
              LCD_OSDOVCN_OCR1_OSD = 0x00000004,
              LCD_OSDOVCN_OCR1_VIDEOANDOSD = 0x00000008} 
             LCD_OSDOVCN_OCR1;              /* FIFO2 data width per-transfer */   
typedef enum {LCD_OSDOVCN_OCR0_VIDEO, 
              LCD_OSDOVCN_OCR0_OSD,
              LCD_OSDOVCN_OCR0_VIDEOANDOSD} 
             LCD_OSDOVCN_OCR0;              /* FIFO2 data width per-transfer */                

/************************************* 
   Macro Declarations
*************************************/
#if 0
($) #define AddMappingEntry(entry, lutEntry) outpb(LCD_LUTENTY1 + (entry), (value))
($) #define RemoveMappingEntry(entry) outpb(LCD_LUTENTY1 + (entry), 0x0)
#endif

#define WriteLUT(entry, value) outpw(REG_LCD_LUTADDR + ((entry) << 2), (value))
#define ReadLUT(entry) inpw(REG_LCD_LUTADDR + ((entry) << 2))

struct w90p710fb_rgb {
    struct fb_bitfield		red;
    struct fb_bitfield		green;
    struct fb_bitfield		blue;
    struct fb_bitfield		transp;
};

struct w90p710fb_lcd_reg {
    unsigned long lcdcon;
    unsigned long lcdfifo;
    unsigned long lcdfifo1para;
    unsigned long lcdfifo1saddr;
    unsigned long lcdfifo1count;    
};

struct w90p710fb_mach_info {
    u_long		pixclock;

    u_short		xres;
    u_short		yres;

    u_char		bpp;
    u_char		hsync_len;
    u_char		left_margin;
    u_char		right_margin;

    u_char		vsync_len;
    u_char		upper_margin;
    u_char		lower_margin;
    u_char		sync;

    u_int		cmap_grayscale:1,
    			cmap_inverse:1,
				cmap_static:1,
		        unused:29;
    u_int		state;

	struct w90p710fb_lcd_reg reg;
#if 0
    unsigned long redlut;
    unsigned long greenlut;
    unsigned long bluelut;

    unsigned long dithmode;
    unsigned long tpal;
#endif
};

#define RGB_8	(0)
#define RGB_16	(1)
#define RGB_24  (2)

#define NR_RGB	3

struct w90p710fb_info {
    struct fb_info		fb;

    signed int			currcon;

    struct w90p710fb_rgb	*rgb[NR_RGB];

    u_int			max_bpp;
    u_int			max_xres;
    u_int			max_yres;

    dma_addr_t		map_dma;
    u_char *		map_cpu;
    u_int			map_size;

    u_char *		screen_cpu;
    dma_addr_t		screen_dma;
    
    u16 *			palette_cpu;
    dma_addr_t		palette_dma; 
    u_int			palette_size;

    u_int			cmap_inverse:1,
    				cmap_static:1,
					unused:30;
    struct w90p710fb_lcd_reg reg;

};

#define outpb(port,value)     (*((UINT8   volatile*)(port))=value)
#define inpb(port)            (*((UINT8   volatile*)(port)))
#define outphw(port,value)    (*((UINT16  volatile*)(port))=value)
#define inphw(port)           (*((UINT16  volatile*)(port)))
#define outpw(port,value)     (*((UINT32  volatile*)(port))=value)
#define inpw(port)            (*((UINT32  volatile*)(port)))

#define W90P710_NAME		"W90P710"

#define MIN_XRES	64
#define MIN_YRES	64