w90p710_lcd.h

winbond w90p710 lcd frame buffer driver。

/****************************************************************************
 *                                                                                    
 * Copyright (c) 2004 - 2004 Winbond Electronics Corp. All rights reserved.           
 *                                                                                    
 ***************************************************************************/
 
/****************************************************************************
 * 
 * FILENAME
 *     lcd_controller.h
 *
 * VERSION
 *     1.0
 *
 * DESCRIPTION
 *     The header file for LCD Controller.
 *
 * DATA STRUCTURES
 *     None
 *
 * FUNCTIONS
 *     None
 *
 * HISTORY
 *     12/??/04		 Ver 1.0 Created by PC33 WCCHEN7
 *
 * REMARK
 *     None
 *
 **************************************************************************/

#define LCD_BA    		0xFFF08000 /* Display, LCM Interface & Bypass */
#define SSP_BA    		0xFFF86200 /* Synchronous Serial Port */
#define GPIO_BA			0xFFF83000

#define UINT8 		unsigned char
#define UINT16 	unsigned short
#define UINT32 	unsigned int

#define REG_GPIO_CFG1			((GPIO_BA+0x0010))
#define REG_GPIO_CFG2			((GPIO_BA+0x0020))
#define REG_GPIO_CFG5			((GPIO_BA+0x0050))
#define REG_GPIO_CFG6			((GPIO_BA+0x0060))

/* Select color depth */
#define CONFIG_W90P710_LCD_TFT_16BPP
//#define CONFIG_W90P710_LCD_STN_16BPP

#ifdef CONFIG_W90P710_LCD_TFT
#ifdef CONFIG_W90P710_LCD_TFT_CASIO
#define FB_X_RES       480
#define FB_Y_RES       240
#endif

#ifdef CONFIG_W90P710_LCD_TFT_AUO960240
#define FB_X_RES       960
#define FB_Y_RES       240
#endif

#ifdef CONFIG_W90P710_LCD_TFT_TOPPOLY240320
#define FB_X_RES       240
#define FB_Y_RES       320
#endif

#ifdef CONFIG_W90P710_LCD_TFT_LG
#define FB_X_RES       640
#define FB_Y_RES       480
#endif
#endif

#ifdef CONFIG_W90P710_LCD_STN
#define FB_X_RES       320
#define FB_Y_RES       240
#endif



#ifdef CONFIG_W90P710_LCD_TFT_24BPP
#define FB_BPP         24
#define BURSTY			1
#endif
#if defined(CONFIG_W90P710_LCD_TFT_16BPP ) || defined(CONFIG_W90P710_LCD_STN_16BPP)
#define FB_BPP         16
#define BURSTY		    1 << 1
#endif
#if defined(CONFIG_W90P710_LCD_TFT_8BPP) || defined(CONFIG_W90P710_LCD_STN_8BPP)
#define FB_BPP         8
#define BURSTY			1 << 2
#endif
#if defined(CONFIG_W90P710_LCD_TFT_4BPP) || defined(CONFIG_W90P710_LCD_STN_4BPP)
#define FB_BPP         4
#define BURSTY			1 << 3
#endif
#if defined(CONFIG_W90P710_LCD_TFT_2BPP) || defined(CONFIG_W90P710_LCD_STN_2BPP)
#define FB_BPP         2
#define BURSTY			1 << 4
#endif
#if defined(CONFIG_W90P710_LCD_TFT_1BPP) || defined(CONFIG_W90P710_LCD_STN_1BPP)
#define FB_BPP         1
#define BURSTY			1 << 5
#endif

#define TRANSBURSTY (FB_X_RES / BURSTY)


#if defined(CONFIG_W90P710_LCD_TFT_24BPP) || defined(CONFIG_W90P710_LCD_TFT_18BPP)
#define FB_Size (FB_X_RES * FB_Y_RES * 32 / 8)
#else
#define FB_Size (FB_X_RES * FB_Y_RES * FB_BPP / 8)
#endif

/**********************************************************************************************************
 *                                                               
 * Universal Serial Interface Control Registers  
 *
 **********************************************************************************************************/
#define	REG_USI_CNTRL		(SSP_BA+0x0)     /* Control and Status Register */
#define	REG_USI_DIVIDER		(SSP_BA+0x04)    /* Clock Divider Register */
#define	REG_USI_SSR			(SSP_BA+0x08)    /* Slave Select Register */
#define	REG_USI_Rx0			(SSP_BA+0x10)    /* Data Receive Register 0 */
#define	REG_USI_Rx1			(SSP_BA+0x14)    /* Data Receive Register 1 */
#define	REG_USI_Rx2			(SSP_BA+0x18)    /* Data Receive Register 2 */
#define	REG_USI_Rx3			(SSP_BA+0x1C)    /* Data Receive Register 3 */
#define	REG_USI_Tx0			(SSP_BA+0x10)    /* Data Transmit Register 0 */
#define	REG_USI_Tx1			(SSP_BA+0x14)    /* Data Transmit Register 1 */
#define	REG_USI_Tx2			(SSP_BA+0x18)    /* Data Transmit Register 2 */
#define	REG_USI_Tx3			(SSP_BA+0x1C)    /* Data Transmit Register 3 */

/****************************************************************************************************
 *
 * 710 LCD Controller Register Sets
 *
 ****************************************************************************************************/
/* LCD Controller */
#define REG_LCD_LCDCON           (LCD_BA+0x0000)   /* LCD Controller control register */

/* LCD Interrupt Control */
#define REG_LCD_LCDINTENB        (LCD_BA+0x0004)   /* LCD interrupt enable register */
#define REG_LCD_LCDINTS          (LCD_BA+0x0008)   /* LCD interrupt status register */
#define REG_LCD_LCDINTC          (LCD_BA+0x000C)   /* LCD interrupt clear register */
                            
/* LCD Pre-processing */    
#define REG_LCD_OSDUPSCF         (LCD_BA+0x0010)   /* OSD data Horizontal/Vertical up-scaling factor */
#define REG_LCD_VDUPSCF          (LCD_BA+0x0014)   /* Video data Horizontal/Vertical up-scaling factor */
#define REG_LCD_OSDNSCF          (LCD_BA+0x0018)   /* OSD data Horizontal/Vertical down-scaling factor */
#define REG_LCD_VDDNSCF          (LCD_BA+0x001C)   /* Video data Horizontal/Vertical down-scaling factor */
                            
/* LCD FIFO Control */      
#define REG_LCD_FIFOCON          (LCD_BA+0x0020)   /* LCD FIFOs controller register */
#define REG_LCD_FIFOSTATUS       (LCD_BA+0x0024)   /* LCD FIFOs status register */
#define REG_LCD_FIFO1PRM         (LCD_BA+0x0028)   /* LCD FIFO1 transfer parameters */
#define REG_LCD_FIFO2PRM         (LCD_BA+0x002C)   /* LCD FIFO2 transfer parameters */
#define REG_LCD_F1SADDR          (LCD_BA+0x0030)   /* FIFO1 transfer data source start address */
#define REG_LCD_F2SADDR          (LCD_BA+0x0034)   /* FIFO2 transfer data source start address */
#define REG_LCD_F1DREQCNT        (LCD_BA+0x0038)   /* FIFO1 transfer data count register */
#define REG_LCD_F2DREQCNT        (LCD_BA+0x003C)   /* FIFO2 transfer data count register */
#define REG_LCD_F1CURADR         (LCD_BA+0x0040)   /* FIFO1 current access data address register */
#define REG_LCD_F2CURADR         (LCD_BA+0x0044)   /* FIFO2 current access data address register */
#define REG_LCD_FIFO1RELACOLCNT   (LCD_BA+0x0048)   /* FIFO 1 real column count register */
#define REG_LCD_FIFO2RELACOLCNT  (LCD_BA+0x004C)   /* FIFO 2 real column count register */

/* Color Generation */
#define REG_LCD_LUTENTY1         (LCD_BA+0x0050)   /* TFT: lookup table entry index register */
#define REG_LCD_LUTENTY2         (LCD_BA+0x0054)   /* TFT: lookup table entry index register */
#define REG_LCD_LUTENTY3         (LCD_BA+0x0058)   /* TFT: lookup table entry index register */
#define REG_LCD_LUTENTY4         (LCD_BA+0x005C)   /* TFT: lookup table entry index register */

#define REG_LCD_OSDLUTENTY1      (LCD_BA+0x0060)   /* TFT: lookup table entry index register */
#define REG_LCD_OSDLUTENTY2      (LCD_BA+0x0064)   /* TFT: lookup table entry index register */
#define REG_LCD_OSDLUTENTY3      (LCD_BA+0x0068)   /* TFT: lookup table entry index register */
#define REG_LCD_OSDLUTENTY4      (LCD_BA+0x006C)   /* TFT: lookup table entry index register */
#define REG_LCD_TMDDITHP1        (LCD_BA+0x0070)   /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP2        (LCD_BA+0x0074)   /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP3        (LCD_BA+0x0078)   /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP4        (LCD_BA+0x007C)   /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP5        (LCD_BA+0x0080)   /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP6        (LCD_BA+0x0084)   /* Gray level dithered data duty pattern */
#define REG_LCD_TMDDITHP7        (LCD_BA+0x0088)   /* Gray level dithered data duty pattern */
                             
/* LCD Post-processing */    
#define REG_LCD_DDISPCP          (LCD_BA+0x0090)   /* Dummy Display Color Pattern Register */
#define REG_LCD_DISPWINS         (LCD_BA+0x0094)   /* Valid Display Window Starting Coordinate */
#define REG_LCD_DISPWINE         (LCD_BA+0x0098)   /* Valid Display Window Ending Coordinate */
#define REG_LCD_OSDWINS          (LCD_BA+0x009C)   /* OSD Window Starting Coordinate */
#define REG_LCD_OSDWINE          (LCD_BA+0x00A0)   /* OSD Window Ending Coordinate */
#define REG_LCD_OSDOVCN          (LCD_BA+0x00A4)   /* OSD Overlay Control Register */
#define REG_LCD_OSDKYP           (LCD_BA+0x00A8)   /* OSD Overlay Color-Key Pattern */
#define REG_LCD_OSDKYM           (LCD_BA+0x00AC)   /* OSD Overlay Color-Key Mask */

/* LCD Timing Generation */
#define REG_LCD_LCDTCON1         (LCD_BA+0x00B0)   /* LCD Timing Control Register 1 */
#define REG_LCD_LCDTCON2         (LCD_BA+0x00B4)   /* LCD Timing Control Register 2 */
#define REG_LCD_LCDTCON3         (LCD_BA+0x00B8)   /* LCD Timing Control Register 3 */
#define REG_LCD_LCDTCON4         (LCD_BA+0x00BC)   /* LCD Timing Control Register 4 */
#define REG_LCD_LCDTCON5         (LCD_BA+0x00C0)   /* LCD Timing Control Register 5 */
#define REG_LCD_LCDTCON6         (LCD_BA+0x00C4)   /* LCD Timing Control Register 6 */
                             
/* Look Up Table SRAM */     
#define REG_LCD_LUTADDR          (LCD_BA+0x0100)   /* The start address of Look-Up Table. 
                                                      The memory range is 0x100 ~ 0x4FF. */
/************************************* 
   710 LCD Controller Register Sets 
   - Bits Definition
*************************************/
#define LCD_LCDCON_PPRST     0x20000000     /* LCD Pre-Processor Reset */
#define LCD_LCDCON_LCDRST    0x10000000     /* LCD Controller Reset(except Control Registers) */
#define LCD_LCDCON_LUTWREN   0x04000000     /* Look Up Table SRAM Read/Write Enable */
#define LCD_LCDCON_OSDEN     0x02000000     /* OSD Data Fetch Control */
#define LCD_LCDCON_LCDCEN    0x01000000     /* LCD Controller Enable */
#define LCD_LCDCON_LCDMON8   0x00800000     /* Monochrome LCD has an 8-bit interface */
#define LCD_LCDCON_LCDBW     0x00400000     /* STN LCD is monochrome */
#define LCD_LCDCON_YUVNRGB   0x00200000     /* Image stored in memory device is YUV format or RGB format */
#define LCD_LCDCON_TVEN      0x00100000     /* External TV encoder Enable */
typedef enum {LCD_LCDCON_CASIOSHOWTYPE_R1G1B2R2G3B3 = 0x00000000,
              LCD_LCDCON_CASIOSHOWTYPE_R1G2B3R4G5B6 = 0x00040000, 
              LCD_LCDCON_CASIOSHOWTYPE_R1G1B1R2G2B2 = 0x00080000} 
             LCD_LCDCON_CASIOSHOWTYPE;             /* NEW */
#define LCD_LCDCON_LCDTFTTYPE  0x00020000     /* CASIO LCD */
#define LCD_LCDCON_LCDTFT    0x00010000     /* LCD is TFT */
//#define LCD_LCDCON_LUTEN     0x00020000     /* Look Up Table Enable */
typedef enum {LCD_LCDCON_LCDSEQ_UYVY = 0x00000000,
              LCD_LCDCON_LCDSEQ_YUYV = 0x00001000, 
              LCD_LCDCON_LCDSEQ_VYUY = 0x00002000,              
              LCD_LCDCON_LCDSEQ_YVYU = 0x00003000}