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📄 pan.rpt

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  _EQ010 = !_LC1_C17 & !_LC3_C17 &  _LC4_C17 &  _LC7_C17;

-- Node name is ':47' 
-- Equation name is '_LC4_C17', type is buried 
_LC4_C17 = DFFE( _EQ011, GLOBAL( CLK), GLOBAL(!CLR),  VCC, !_LC1_C23);
  _EQ011 =  _LC4_C17 & !_LC6_C17 & !_LC8_C17
         # !_LC4_C17 & !_LC6_C17 &  _LC8_C17;

-- Node name is ':48' 
-- Equation name is '_LC3_C17', type is buried 
_LC3_C17 = DFFE( _EQ012, GLOBAL( CLK), GLOBAL(!CLR),  VCC, !_LC1_C23);
  _EQ012 =  _LC3_C17 & !_LC5_C17 & !_LC6_C17
         # !_LC3_C17 &  _LC5_C17 & !_LC6_C17;

-- Node name is ':49' 
-- Equation name is '_LC1_C17', type is buried 
_LC1_C17 = DFFE( _EQ013, GLOBAL( CLK), GLOBAL(!CLR),  VCC, !_LC1_C23);
  _EQ013 =  _LC1_C17 & !_LC6_C17 & !_LC7_C17
         # !_LC1_C17 & !_LC6_C17 &  _LC7_C17;

-- Node name is ':50' 
-- Equation name is '_LC7_C17', type is buried 
_LC7_C17 = DFFE(!_LC7_C17, GLOBAL( CLK), GLOBAL(!CLR),  VCC, !_LC1_C23);

-- Node name is ':55' 
-- Equation name is '_LC8_C21', type is buried 
_LC8_C21 = LCELL( _EQ014);
  _EQ014 =  _LC1_C21 &  _LC2_C17 & !_LC5_C21 & !_LC7_C21;

-- Node name is '~72~1' 
-- Equation name is '~72~1', location is LC2_C23, type is buried.
-- synthesized logic cell 
_LC2_C23 = LCELL( _EQ015);
  _EQ015 =  _LC6_C17 & !_LC8_C21;

-- Node name is ':72' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = LCELL( _EQ016);
  _EQ016 =  _LC1_C21 &  _LC2_C23 & !_LC4_C21
         #  _LC1_C21 &  _LC2_C23 & !_LC7_C21
         # !_LC1_C21 &  _LC2_C23 &  _LC4_C21 &  _LC7_C21;

-- Node name is ':73' 
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = LCELL( _EQ017);
  _EQ017 =  _LC2_C23 & !_LC5_C21 &  _LC7_C21
         # !_LC2_C17 &  _LC2_C23 &  _LC7_C21
         #  _LC2_C17 &  _LC2_C23 &  _LC5_C21 & !_LC7_C21;

-- Node name is ':74' 
-- Equation name is '_LC2_C21', type is buried 
_LC2_C21 = LCELL( _EQ018);
  _EQ018 = !_LC2_C17 &  _LC2_C23 &  _LC5_C21
         #  _LC2_C17 &  _LC2_C23 & !_LC5_C21;

-- Node name is ':86' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = DFFE( _EQ019, GLOBAL( CLK), GLOBAL(!CLR),  VCC, !_LC1_C23);
  _EQ019 =  _LC6_C21
         #  _LC1_C21 & !_LC6_C17;

-- Node name is ':87' 
-- Equation name is '_LC7_C21', type is buried 
_LC7_C21 = DFFE( _EQ020, GLOBAL( CLK), GLOBAL(!CLR),  VCC, !_LC1_C23);
  _EQ020 =  _LC3_C21
         # !_LC6_C17 &  _LC7_C21;

-- Node name is ':88' 
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = DFFE( _EQ021, GLOBAL( CLK), GLOBAL(!CLR),  VCC, !_LC1_C23);
  _EQ021 =  _LC2_C21
         #  _LC5_C21 & !_LC6_C17;

-- Node name is ':89' 
-- Equation name is '_LC2_C17', type is buried 
_LC2_C17 = DFFE( _EQ022, GLOBAL( CLK), GLOBAL(!CLR),  VCC, !_LC1_C23);
  _EQ022 =  _LC2_C17 & !_LC6_C17
         # !_LC2_C17 &  _LC6_C17;

-- Node name is ':104' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = LCELL( _EQ023);
  _EQ023 = !_LC1_B18 & !_LC3_B18 &  _LC5_B18 &  _LC7_B18;

-- Node name is ':120' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = LCELL( _EQ024);
  _EQ024 = !_LC1_A13 &  _LC4_A13 &  _LC5_A13 & !_LC8_A13;

-- Node name is ':137' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = DFFE( _EQ025,  cn1, GLOBAL(!CLR),  VCC,  VCC);
  _EQ025 = !_LC4_A13 &  _LC5_A13
         #  _LC1_A13 &  _LC4_A13 & !_LC5_A13 &  _LC8_A13
         # !_LC1_A13 &  _LC5_A13 &  _LC8_A13
         #  _LC1_A13 &  _LC5_A13 & !_LC8_A13;

-- Node name is ':138' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = DFFE( _EQ026,  cn1, GLOBAL(!CLR),  VCC,  VCC);
  _EQ026 = !_LC1_A13 &  _LC8_A13
         # !_LC4_A13 &  _LC8_A13
         #  _LC1_A13 &  _LC4_A13 & !_LC8_A13;

-- Node name is ':139' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = DFFE( _EQ027,  cn1, GLOBAL(!CLR),  VCC,  VCC);
  _EQ027 =  _LC1_A13 & !_LC4_A13
         # !_LC1_A13 &  _LC4_A13 &  _LC8_A13
         # !_LC1_A13 &  _LC4_A13 & !_LC5_A13;

-- Node name is ':140' 
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = DFFE(!_LC4_A13,  cn1, GLOBAL(!CLR),  VCC,  VCC);

-- Node name is ':142' 
-- Equation name is '_LC3_B18', type is buried 
_LC3_B18 = DFFE( _EQ028,  cn1, GLOBAL(!CLR),  VCC,  _LC6_A13);
  _EQ028 =  _LC3_B18 & !_LC4_B18 & !_LC8_B18
         # !_LC3_B18 & !_LC4_B18 &  _LC8_B18;

-- Node name is ':143' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = DFFE( _EQ029,  cn1, GLOBAL(!CLR),  VCC,  _LC6_A13);
  _EQ029 = !_LC4_B18 & !_LC6_B18 &  _LC7_B18
         # !_LC4_B18 &  _LC6_B18 & !_LC7_B18;

-- Node name is ':144' 
-- Equation name is '_LC1_B18', type is buried 
_LC1_B18 = DFFE( _EQ030,  cn1, GLOBAL(!CLR),  VCC,  _LC6_A13);
  _EQ030 =  _LC1_B18 & !_LC4_B18 & !_LC5_B18
         # !_LC1_B18 & !_LC4_B18 &  _LC5_B18;

-- Node name is ':145' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = DFFE(!_LC5_B18,  cn1, GLOBAL(!CLR),  VCC,  _LC6_A13);

-- Node name is ':158' 
-- Equation name is '_LC1_B11', type is buried 
!_LC1_B11 = _LC1_B11~NOT;
_LC1_B11~NOT = LCELL( _EQ031);
  _EQ031 =  _LC2_B11
         #  _LC3_B11
         # !_LC6_B11
         # !_LC4_B11;

-- Node name is ':174' 
-- Equation name is '_LC1_B6', type is buried 
_LC1_B6  = LCELL( _EQ032);
  _EQ032 = !_LC2_B6 &  _LC3_B6 &  _LC6_B6 & !_LC8_B6;

-- Node name is ':191' 
-- Equation name is '_LC3_B6', type is buried 
_LC3_B6  = DFFE( _EQ033,  cn2, GLOBAL(!CLR),  VCC,  VCC);
  _EQ033 =  _LC3_B6 & !_LC6_B6
         #  _LC2_B6 & !_LC3_B6 &  _LC6_B6 &  _LC8_B6
         #  _LC2_B6 &  _LC3_B6 & !_LC8_B6
         # !_LC2_B6 &  _LC3_B6 &  _LC8_B6;

-- Node name is ':192' 
-- Equation name is '_LC2_B6', type is buried 
_LC2_B6  = DFFE( _EQ034,  cn2, GLOBAL(!CLR),  VCC,  VCC);
  _EQ034 =  _LC2_B6 & !_LC8_B6
         #  _LC2_B6 & !_LC6_B6
         # !_LC2_B6 &  _LC6_B6 &  _LC8_B6;

-- Node name is ':193' 
-- Equation name is '_LC8_B6', type is buried 
_LC8_B6  = DFFE( _EQ035,  cn2, GLOBAL(!CLR),  VCC,  VCC);
  _EQ035 = !_LC6_B6 &  _LC8_B6
         #  _LC2_B6 &  _LC6_B6 & !_LC8_B6
         # !_LC3_B6 &  _LC6_B6 & !_LC8_B6;

-- Node name is ':194' 
-- Equation name is '_LC6_B6', type is buried 
_LC6_B6  = DFFE(!_LC6_B6,  cn2, GLOBAL(!CLR),  VCC,  VCC);

-- Node name is ':196' 
-- Equation name is '_LC3_B11', type is buried 
_LC3_B11 = DFFE( _EQ036,  cn2, GLOBAL(!CLR),  VCC,  _LC1_B6);
  _EQ036 = !_LC1_B11 &  _LC3_B11 & !_LC7_B11
         # !_LC1_B11 & !_LC3_B11 &  _LC7_B11;

-- Node name is ':197' 
-- Equation name is '_LC6_B11', type is buried 
_LC6_B11 = DFFE( _EQ037,  cn2, GLOBAL(!CLR),  VCC,  _LC1_B6);
  _EQ037 = !_LC1_B11 & !_LC5_B11 &  _LC6_B11
         # !_LC1_B11 &  _LC5_B11 & !_LC6_B11;

-- Node name is ':198' 
-- Equation name is '_LC2_B11', type is buried 
_LC2_B11 = DFFE( _EQ038,  cn2, GLOBAL(!CLR),  VCC,  _LC1_B6);
  _EQ038 = !_LC1_B11 &  _LC2_B11 & !_LC4_B11
         # !_LC1_B11 & !_LC2_B11 &  _LC4_B11;

-- Node name is ':199' 
-- Equation name is '_LC4_B11', type is buried 
_LC4_B11 = DFFE(!_LC4_B11,  cn2, GLOBAL(!CLR),  VCC,  _LC1_B6);



Project Information                   d:\program files\myeda\myverilog\pan.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,621K

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