📄 pan.rpt
字号:
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\program files\myeda\myverilog\pan.rpt
pan
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 17 AND2 0 2 0 1 |lpm_add_sub:204|addcore:adder|:55
- 8 - C 17 AND2 0 3 0 1 |lpm_add_sub:204|addcore:adder|:59
- 4 - C 21 AND2 0 2 0 1 |lpm_add_sub:205|addcore:adder|:55
- 6 - B 18 AND2 0 2 0 1 |lpm_add_sub:206|addcore:adder|:55
- 8 - B 18 AND2 0 3 0 1 |lpm_add_sub:206|addcore:adder|:59
- 5 - B 11 AND2 0 2 0 1 |lpm_add_sub:208|addcore:adder|:55
- 7 - B 11 AND2 0 3 0 1 |lpm_add_sub:208|addcore:adder|:59
- 1 - C 23 SOFT s ! 1 0 0 9 PAUSE~1
- 6 - C 17 AND2 0 4 0 9 :28
- 4 - C 17 DFFE + 0 3 1 1 :47
- 3 - C 17 DFFE + 0 3 1 2 :48
- 1 - C 17 DFFE + 0 3 1 3 :49
- 7 - C 17 DFFE + 0 1 1 4 :50
- 8 - C 21 AND2 0 4 0 2 :55
- 2 - C 23 AND2 s 0 2 0 3 ~72~1
- 6 - C 21 OR2 0 4 0 1 :72
- 3 - C 21 OR2 0 4 0 1 :73
- 2 - C 21 OR2 0 3 0 1 :74
- 1 - C 21 DFFE + 0 3 1 2 :86
- 7 - C 21 DFFE + 0 3 1 3 :87
- 5 - C 21 DFFE + 0 3 1 4 :88
- 2 - C 17 DFFE + 0 2 1 4 :89
- 3 - C 23 DFFE + 0 3 0 9 cn1 (:102)
- 4 - B 18 AND2 0 4 0 4 :104
- 6 - A 13 AND2 0 4 0 5 :120
- 5 - A 13 DFFE 0 4 1 2 :137
- 8 - A 13 DFFE 0 3 1 3 :138
- 1 - A 13 DFFE 0 4 1 3 :139
- 4 - A 13 DFFE 0 1 1 4 :140
- 3 - B 18 DFFE 0 4 1 1 :142
- 7 - B 18 DFFE 0 4 1 2 :143
- 1 - B 18 DFFE 0 4 1 3 :144
- 5 - B 18 DFFE 0 2 1 4 :145
- 2 - B 18 DFFE 0 3 0 8 cn2 (:157)
- 1 - B 11 OR2 ! 0 4 0 3 :158
- 1 - B 06 AND2 0 4 0 4 :174
- 3 - B 06 DFFE 0 4 1 2 :191
- 2 - B 06 DFFE 0 3 1 3 :192
- 8 - B 06 DFFE 0 4 1 3 :193
- 6 - B 06 DFFE 0 1 1 4 :194
- 3 - B 11 DFFE 0 4 1 1 :196
- 6 - B 11 DFFE 0 4 1 2 :197
- 2 - B 11 DFFE 0 4 1 3 :198
- 4 - B 11 DFFE 0 2 1 4 :199
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\program files\myeda\myverilog\pan.rpt
pan
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 5/ 96( 5%) 4/ 48( 8%) 2/ 48( 4%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 5/ 96( 5%) 0/ 48( 0%) 7/ 48( 14%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\program files\myeda\myverilog\pan.rpt
pan
** CLOCK SIGNALS **
Type Fan-out Name
DFF 10 cn1
INPUT 9 CLK
DFF 9 cn2
Device-Specific Information: d:\program files\myeda\myverilog\pan.rpt
pan
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 26 CLR
Device-Specific Information: d:\program files\myeda\myverilog\pan.rpt
pan
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
PAUSE : INPUT;
-- Node name is ':102' = 'cn1'
-- Equation name is 'cn1', location is LC3_C23, type is buried.
cn1 = DFFE( _EQ001, GLOBAL( CLK), GLOBAL(!CLR), VCC, !_LC1_C23);
_EQ001 = cn1 & _LC6_C17
# _LC6_C17 & _LC8_C21;
-- Node name is ':157' = 'cn2'
-- Equation name is 'cn2', location is LC2_B18, type is buried.
cn2 = DFFE( _EQ002, cn1, GLOBAL(!CLR), VCC, VCC);
_EQ002 = cn2 & _LC6_A13
# _LC4_B18 & _LC6_A13;
-- Node name is 'MH0'
-- Equation name is 'MH0', type is output
MH0 = _LC4_B11;
-- Node name is 'MH1'
-- Equation name is 'MH1', type is output
MH1 = _LC2_B11;
-- Node name is 'MH2'
-- Equation name is 'MH2', type is output
MH2 = _LC6_B11;
-- Node name is 'MH3'
-- Equation name is 'MH3', type is output
MH3 = _LC3_B11;
-- Node name is 'ML0'
-- Equation name is 'ML0', type is output
ML0 = _LC6_B6;
-- Node name is 'ML1'
-- Equation name is 'ML1', type is output
ML1 = _LC8_B6;
-- Node name is 'ML2'
-- Equation name is 'ML2', type is output
ML2 = _LC2_B6;
-- Node name is 'ML3'
-- Equation name is 'ML3', type is output
ML3 = _LC3_B6;
-- Node name is 'MSH0'
-- Equation name is 'MSH0', type is output
MSH0 = _LC2_C17;
-- Node name is 'MSH1'
-- Equation name is 'MSH1', type is output
MSH1 = _LC5_C21;
-- Node name is 'MSH2'
-- Equation name is 'MSH2', type is output
MSH2 = _LC7_C21;
-- Node name is 'MSH3'
-- Equation name is 'MSH3', type is output
MSH3 = _LC1_C21;
-- Node name is 'MSL0'
-- Equation name is 'MSL0', type is output
MSL0 = _LC7_C17;
-- Node name is 'MSL1'
-- Equation name is 'MSL1', type is output
MSL1 = _LC1_C17;
-- Node name is 'MSL2'
-- Equation name is 'MSL2', type is output
MSL2 = _LC3_C17;
-- Node name is 'MSL3'
-- Equation name is 'MSL3', type is output
MSL3 = _LC4_C17;
-- Node name is 'PAUSE~1'
-- Equation name is 'PAUSE~1', location is LC1_C23, type is buried.
-- synthesized logic cell
!_LC1_C23 = _LC1_C23~NOT;
_LC1_C23~NOT = LCELL(!PAUSE);
-- Node name is 'SH0'
-- Equation name is 'SH0', type is output
SH0 = _LC5_B18;
-- Node name is 'SH1'
-- Equation name is 'SH1', type is output
SH1 = _LC1_B18;
-- Node name is 'SH2'
-- Equation name is 'SH2', type is output
SH2 = _LC7_B18;
-- Node name is 'SH3'
-- Equation name is 'SH3', type is output
SH3 = _LC3_B18;
-- Node name is 'SL0'
-- Equation name is 'SL0', type is output
SL0 = _LC4_A13;
-- Node name is 'SL1'
-- Equation name is 'SL1', type is output
SL1 = _LC1_A13;
-- Node name is 'SL2'
-- Equation name is 'SL2', type is output
SL2 = _LC8_A13;
-- Node name is 'SL3'
-- Equation name is 'SL3', type is output
SL3 = _LC5_A13;
-- Node name is '|lpm_add_sub:204|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = LCELL( _EQ003);
_EQ003 = _LC1_C17 & _LC7_C17;
-- Node name is '|lpm_add_sub:204|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C17', type is buried
_LC8_C17 = LCELL( _EQ004);
_EQ004 = _LC1_C17 & _LC3_C17 & _LC7_C17;
-- Node name is '|lpm_add_sub:205|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = LCELL( _EQ005);
_EQ005 = _LC2_C17 & _LC5_C21;
-- Node name is '|lpm_add_sub:206|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = LCELL( _EQ006);
_EQ006 = _LC1_B18 & _LC5_B18;
-- Node name is '|lpm_add_sub:206|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B18', type is buried
_LC8_B18 = LCELL( _EQ007);
_EQ007 = _LC1_B18 & _LC5_B18 & _LC7_B18;
-- Node name is '|lpm_add_sub:208|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ008);
_EQ008 = _LC2_B11 & _LC4_B11;
-- Node name is '|lpm_add_sub:208|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = LCELL( _EQ009);
_EQ009 = _LC2_B11 & _LC4_B11 & _LC6_B11;
-- Node name is ':28'
-- Equation name is '_LC6_C17', type is buried
_LC6_C17 = LCELL( _EQ010);
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