pan.v

数字秒表

module pan(CLK,CLR,PAUSE,MSH,MSL,SH,SL,MH,ML);
input CLK,CLR;
input PAUSE;
output[3:0] MSH,MSL,SH,SL,MH,ML;
reg[3:0] MSH,MSL,SH,SL,MH,ML;
reg cn1,cn2; 

always @(posedge CLR or posedge CLK)
begin
	if(CLR) 
	   begin MSH<=0;MSL<=0;cn1<=0;end
	 else if(!PAUSE) 
	    begin if(MSL==9) begin MSL<=0;      
	           if(MSH==9) begin MSH<=0; cn1<=1; end //毫秒加到100，进位给秒cn1，并且清零
	            else MSH<=MSH+1; end
	           else begin MSL<=MSL+1; cn1<=0;end    //毫秒加1
	end 
end

always @(posedge CLR or posedge cn1)
begin
   if(CLR) 
	  begin SH<=0;SL<=0;cn2<=0;end
	else if(SL==9) begin SL<=0;
	      if(SH==5) begin SH<=0; cn2<=1; end //秒加到59，进位给分cn2，并且清零
	       else SH<=SH+1;end
	      else begin SL<=SL+1; cn2<=0; end    // 秒加1
end


always @(posedge CLR or posedge cn2)
begin 
	if(CLR)
	   begin MH<=0;ML<=0; end 
	 else if(ML==9) begin ML<=0;
	       if(MH==5) MH<=0;    //分加到59，清零
	        else MH<=MH+1;end
	       else ML<=ML+1;      // 分加1
end
endmodule