📄 mpegimda-60.a
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S 2,d0,d3 move.l d3,1*4(a3) S 3,d0,d3 move.l d3,2*4(a3) S 5,d0,d3 move.l d3,3*4(a3) ; 0 M 0,K9,d3 M_SUB 2,K11 M_ADD 3,K5 M_SUB 5,K3 M_SUB 6,K15 M_ADD 8,K17 M_SUB 9,K0 M_ADD 11,K2 M_SUB 12,K14 M_ADD 14,K12 M_ADD 15,K6 M_SUB 17,K8 add.l 0*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 neg.l d4 ; win[ 17 ] can be negated to suppress this line W d3,0 W d4,17 ; 1 MT 0,K10,d3 MT_SUB 1,K16 MT_ADD 2,K1 MT_SUB 3,K7 add.l 1*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 neg.l d4 W d3,1 W d4,16 ; 2 M 0,K11,d3 M_ADD 2,K14 M_ADD 3,K8 M_ADD 5,K17 M_ADD 6,K5 M_SUB 8,K15 M_ADD 9,K2 M_SUB 11,K12 M_ADD 12,K0 M_SUB 14,K9 M_ADD 15,K3 M_SUB 17,K6 add.l 2*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 neg.l d4 W d3,2 W d4,15 ; 3 M 0,K12,d3 M_ADD 2,K9 M_ADD 3,K15 M_ADD 5,K6 M_SUB 6,K17 M_ADD 8,K3 M_SUB 9,K14 M_ADD 11,K0 M_SUB 12,K11 M_ADD 14,K2 M_SUB 15,K8 M_ADD 17,K5 add.l 2*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 neg.l d4 W d3,3 W d4,14 ; 4 MT 0,K13,d3 MT_ADD 1,K4 MT_SUB 2,K13 MT_ADD 3,K4 add.l 1*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 neg.l d4 W d3,4 W d4,13 ; 5 M 0,K14,d3 M_ADD 2,K0 M_SUB 3,K6 M_ADD 5,K15 M_SUB 6,K8 M_SUB 8,K5 M_ADD 9,K12 M_SUB 11,K9 M_ADD 12,K2 M_ADD 14,K11 M_ADD 15,K17 M_ADD 17,K3 add.l 0*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 neg.l d4 W d3,5 W d4,12 ; 6 M 0,K15,d3 M_ADD 2,K5 M_SUB 3,K0 M_SUB 5,K9 M_ADD 6,K14 M_SUB 8,K11 M_ADD 9,K6 M_ADD 11,K3 M_SUB 12,K8 M_ADD 14,K17 M_SUB 15,K12 M_SUB 17,K2 add.l 3*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 neg.l d4 W d3,6 W d4,11 ; 7 MT 0,K16,d3 MT_ADD 1,K10 MT_SUB 2,K7 MT_SUB 3,K1 add.l 4*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 neg.l d4 W d3,7 W d4,10 ; 8 M 0,K17,d3 M_ADD 2,K15 M_SUB 3,K14 M_SUB 5,K12 M_ADD 6,K11 M_ADD 8,K9 M_SUB 9,K8 M_SUB 11,K6 M_ADD 12,K5 M_ADD 14,K3 M_SUB 15,K2 M_SUB 17,K0 add.l 5*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 neg.l d4 W d3,8 W d4,9 ; 9+9 M 0,K8,d3 neg.l d3 M_ADD 2,K6 M_SUB 3,K12 M_ADD 5,K14 M_ADD 6,K2 M_SUB 8,K0 M_SUB 9,K17 M_ADD 11,K15 M_SUB 12,K3 M_ADD 14,K5 M_ADD 15,K11 M_SUB 17,K9 sub.l 3*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 WP d3,18 WP d4,35 ; 10+9 MT 0,K7,d3 neg.l d3 MT_ADD 1,K1 MT_ADD 2,K16 MT_SUB 3,K10 sub.l 4*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 WP d3,19 WP d4,34 ; 11+9 M 0,K6,d3 neg.l d3 M_ADD 2,K3 M_ADD 3,K9 M_SUB 5,K10 M_SUB 6,K12 M_ADD 8,K2 M_ADD 9,K15 M_SUB 11,K5 M_ADD 12,K17 M_ADD 14,K8 M_SUB 15,K14 M_SUB 17,K11 sub.l 5*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 WP d3,20 WP d4,33 ; 12+9 M 0,K5,d3 neg.l d3 M_ADD 2,K8 M_ADD 3,K2 M_SUB 5,K11 M_SUB 6,K0 M_ADD 8,K14 M_ADD 9,K3 M_SUB 11,K17 M_SUB 12,K6 M_SUB 14,K15 M_ADD 15,K9 M_ADD 17,K12 add.l 5*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 WP d3,21 WP d4,32 ; 13+9 MT 0,K4,d3 neg.l d3 MT_ADD 1,K13 MT_ADD 2,K4 MT_ADD 3,K13 add.l 4*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 WP d3,22 WP d4,31 ; 14+9 M 0,K3,d3 neg.l d3 M_SUB 2,K17 M_ADD 3,K11 M_ADD 5,K2 M_ADD 6,K9 M_SUB 8,K12 M_SUB 9,K5 M_SUB 11,K8 M_SUB 12,K15 M_ADD 14,K6 M_ADD 15,K0 M_ADD 17,K14 add.l 3*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 WP d3,23 WP d4,30 ; 15+9 M 0,K2,d3 neg.l d3 M_SUB 2,K12 M_SUB 3,K17 M_ADD 5,K8 M_ADD 6,K3 M_ADD 8,K6 M_ADD 9,K11 M_SUB 11,K14 M_SUB 12,K9 M_SUB 14,K0 M_SUB 15,K5 M_SUB 17,K15 add.l 0*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 WP d3,24 WP d4,29 ; 16+9 MT 0,K1,d3 neg.l d3 MT_SUB 1,K7 MT_SUB 2,K10 MT_SUB 3,K16 add.l 1*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 WP d3,25 WP d4,28 ; 17+9 M 0,K0,d3 neg.l d3 M_SUB 2,K2 M_SUB 3,K3 M_SUB 5,K5 M_SUB 6,K6 M_SUB 8,K8 M_SUB 9,K9 M_SUB 11,K11 M_SUB 12,K12 M_SUB 14,K14 M_SUB 15,K15 M_SUB 17,K17 add.l 2*4(a4),d3 IMDCT_FIX d3 move.l d3,d4 WP d3,26 WP d4,27 move.l a5,a3 unlk a6 rtsK0 set 16244K1 set 15137K2 set 12998K3 set 9974K4 set 6270K5 set 2139; M3 xi, Kx, <dest reg>; performs: ((INT32)x[ xi*3 ] * (Kx));M3 MACRO move.w \1*6(a0),\3 muls.w #\2,\3 ENDM;; M3_ADD xi, Kx; performs: M3 xi, Kx, d0; add.l d0,d3;M3_ADD MACRO M3 \1,\2,d0 add.l d0,d3 ENDM;; M3_SUB xi, Kx; performs: M3 xi, Kx, d0; sub.l d0,d3;M3_SUB MACRO M3 \1,\2,d0 sub.l d0,d3 ENDM; W3 <reg>, wi -> <reg> * win[ wi ] + out[ wi ] -> out[ wi ]; performs: (<reg> * win[ wi ]) >> WIN_BITS + out[ wi ] -> out[ wi ];W3 MACRO muls.w \2*2(a2),\1 asr.l d6,\1 add.w \1,\2*2(a1) ENDM; W31 <reg>, oi, wi -> <reg> * win[ wi ] + prev[ oi ] -> out[ oi*32 ]; performs: (<reg> * win[ wi ]) >> WIN_BITS + prev[ oi ] -> out[ oi*32 ];W31 MACRO muls.w \3*2(a2),\1 asr.l d6,\1 add.w \2*2(a5),\1 move.w \1,\2*2*32(a1) ENDM; W32 <reg>, oi, wi -> <reg> * win[ wi ] -> out[ oi*32 ]; performs: (<reg> * win[ wi ]) >> WIN_BITS -> out[ oi*32 ];W32 MACRO muls.w \3*2(a2),\1 asr.l d6,\1 move.w \1,\2*2*32(a1) ENDM
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