📄 r8c2c2d_2009.c
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/************************************************************************************
* *
* Module file name : r8c2c2d_2009.c *
* Module name : Clock synchronous serial transmission/reception 0 *
* System name : R8C2C/2D(5.0V/20MHz) Basic model3 *
* Module number : R8C2C/2D-2009 *
* *
* Version : 1.00 *
* ROM size : 414byte *
* RAM size : 41byte *
* Contents : - *
* *
************************************************************************************/
/************************************************************
* Include file *
/***********************************************************/
#include "sfr_r8c2c2d.h" /* Definition of the R8C/2C,2D SFR for Sango */
/************************************************************
* Declaration of function prototype *
************************************************************/
void sio_trx5(void); /* R8C2C/2D-2009 Trans/Receive of Clock synchronous serial I/O 0 */
/*** Extern ***/
/*** Static ***/
static void sio_trx5_sfr(void); /* Initial setting of function SFR registers */
static void sio_trx5_exe(void); /* Execute SI/O transmit and receive */
/************************************************************
* Declaration of interrupt *
************************************************************/
void uart0_tra_int_func10(void); /* R8C2C/2D-2009 UART0 transmit interrupt function of Trans/Receive of Clock synchronous serial I/O 0 */
void uart0_rec_int_func14(void); /* R8C2C/2D-2009 UART0 receive interrupt function of Trans/Receive of Clock synchronous serial I/O 0 */
/************************************************************
* Definition of RAM area *
************************************************************/
/*** Input parameters ***/
union byte_def sio_trx5_control;
#define sio_trx5_cont sio_trx5_control.byte /* SI/O control */
#define sio_trx5_brg0 sio_trx5_control.bit.b0 /* SI/O BRG count source select bit0 */
#define sio_trx5_brg1 sio_trx5_control.bit.b1 /* SI/O BRG count source select bit1 */
#define sio_trx5_clk sio_trx5_control.bit.b2 /* SI/O Internal/external clock select bit */
#define sio_trx5_pola sio_trx5_control.bit.b3 /* SI/O clock edge polarity select bit */
#define sio_trx5_form sio_trx5_control.bit.b4 /* SI/O format bit */
#define sio_trx5_wait sio_trx5_control.bit.b5 /* SI/O wait bit : "0" = normal mode , "1" = wait mode*/
#define sio_trx5_trx sio_trx5_control.bit.b6 /* SI/O transmit or receive select bit : "0" = transmit , "1" = receive */
#define sio_trx5_star sio_trx5_control.bit.b7 /* SI/O transmit and receive start bit */
unsigned char sio_trx5_brg; /* SI/O bit rate generator (BRG) */
unsigned char sio_trx5_tx_auto_buf[8]; /* SI/O automatic continuousness transmission buffer */
unsigned char sio_trx5_tx_auto_cnt; /* SI/O automatic continuousness transmission buffer counter */
union byte_def sio_trx5_rece_control;
#define sio_trx5_rx_cont sio_trx5_rece_control.byte /* SI/O receive control */
#define sio_trx5_rx_brg0 sio_trx5_rece_control.bit.b0 /* SI/O receive BRG count source select bit0 */
#define sio_trx5_rx_brg1 sio_trx5_rece_control.bit.b1 /* SI/O receive BRG count source select bit1 */
#define sio_trx5_rx_clk sio_trx5_rece_control.bit.b2 /* SI/O receive Internal/external clock select bit */
#define sio_trx5_rx_pola sio_trx5_rece_control.bit.b3 /* SI/O receive clock edge polarity select bit */
#define sio_trx5_rx_form sio_trx5_rece_control.bit.b4 /* SI/O receive format bit */
#define sio_trx5_rx_err sio_trx5_rece_control.bit.b5 /* SI/O receive error bit */
#define sio_trx5_rx_ena sio_trx5_rece_control.bit.b6 /* SI/O receive enable bit */
#define sio_trx5_rx_star sio_trx5_rece_control.bit.b7 /* SI/O receive start bit */
unsigned char sio_trx5_rx_auto_cnt; /* SI/O automatic continuousness reception buffer counter */
/*** Output parameters ***/
unsigned char sio_trx5_rx_auto_buf[8]; /* SI/O automatic continuousness reception buffer */
/*** Static ***/
static unsigned char c_sio_trx5_wait; /* SI/O wait mode counter */
static unsigned char sio_trx5_tx_data[8]; /* SI/O automatic continuousness transmission buffer for execute */
static unsigned char sio_trx5_tx_cnt; /* SI/O automatic continuousness transmission buffer counter for execute */
static unsigned char sio_trx5_rx_data[8]; /* SI/O automatic continuousness reception buffer for execute */
static unsigned char sio_trx5_rx_cnt; /* SI/O automatic continuousness reception counter for execute */
static union byte_def sio_trx5_sfr_flag; /* SI/O transmit and receive SFR flag */
#define f_sio_trx5_sfr sio_trx5_sfr_flag.bit.b0 /* SFR initial setting flag : "0" = not set , "1" = already set */
/************************************************************
* Definition of base section *
************************************************************/
/************************************************************
* Definition of port *
************************************************************/
/************************************************************
* Data table *
************************************************************/
/************************************************************************************
Name :sio_trx5
Parameters :-
Returns :-
Description :Clock synchronous serial transmission/reception 0
************************************************************************************/
void sio_trx5(void){
unsigned char cnt;
/* Initial setting of fauction SFR */
if(f_sio_trx5_sfr == 0){ /* Has not function SFR been set yet? */
sio_trx5_sfr(); /* Initial setting of function SFR registers */
}
/* SI/O mode select */
if(sio_trx5_wait == 0){ /* Wait mode used? */
/* Normal mode */
sio_trx5_exe(); /* Execute SI/O transmit and receive */
c_sio_trx5_wait = 0; /* SI/O wait mode count clear */
}
else{
/* Wait mode */
if(c_sio_trx5_wait == 0){ /* SI/O wait mode count "0"? */
sio_trx5_exe(); /* Execute SI/O transmit and receive */
}
else{
--c_sio_trx5_wait; /* The SI/O wait mode count is decreased every 250usec */
}
}
}
/************************************************************************************
Name :sio_trx5_exe
Parameters :-
Returns :-
Description :Execute SI/O transmit and receive
************************************************************************************/
static void sio_trx5_exe(void){
unsigned char cnt;
/* SI/O transmit and receive */
if(sio_trx5_star == 1){ /* SI/O transmit and receive start? */
if((te_u0c1 == 0) && (txept_u0c0 == 1)){ /* Transmit disabled? and transmit register empty? */
if((re_u0c1 == 0) && (ri_u0c1 == 0)){ /* Receive disabled? and Rrcive register empty? */
u0brg = sio_trx5_brg; /* BRG set */
ckdir_u0mr = sio_trx5_clk; /* Clock select */
clk0_u0c0 = sio_trx5_brg0; /* BRG count source select */
clk1_u0c0 = sio_trx5_brg1; /* BRG count source select */
ckpol_u0c0 = sio_trx5_pola; /* CLK polarity select */
uform_u0c0 = sio_trx5_form; /* Transfer format select */
if(sio_trx5_trx == 0){ /* SI/O transmit? */
/* Execute SI/O transmit */
for(cnt=0;cnt<=7;cnt++){
sio_trx5_tx_data[cnt]=sio_trx5_tx_auto_buf[cnt];/* SI/O automatic continuousness transmission buffer data set */
}
sio_trx5_tx_cnt = sio_trx5_tx_auto_cnt & 0x07; /* SI/O automatic continuousness transmission buffer counter set(Automatic continuousness reception of 8bytes(maximum)) */
/* %%R8C2C2D-2009-LIN04%% */
s0tic = 0x07;
te_u0c1 = 1; /* Transmit enabled */
u0tbl = sio_trx5_tx_data[sio_trx5_tx_cnt]; /* UART0 transmit buffer register Low : transmit data set(transmit start) */
}
else{
/* Execute SI/O receive */
sio_trx5_rx_cnt = sio_trx5_rx_auto_cnt & 0x07; /* SI/O automatic continuousness reception buffer counter set(Automatic continuousness reception of 8bytes(maximum)) */
/* %%R8C2C2D-2009-LIN05%% */
s0ric = 0x07;
u0tbl = 0xff; /* Dummy data set for receive */
re_u0c1 = 1; /* Receive enabled */
te_u0c1 = 1; /* Transmit enabled */
sio_trx5_rx_ena = 1; /* SI/O recive enabled (for communication synchronization) */
}
}
}
}
}
/************************************************************************************
Name :sio_trx5_sfr
Parameters :-
Returns :-
Description :Initial setting of function SFR registers
************************************************************************************/
static void sio_trx5_sfr(void){
/* Port direction */
pd1_4 = 1; /* Port P1_4(TxD0) direction = output */
pd1_5 = 0; /* Port P1_5(RxD0) direction = input */
/* pd1_6 = 1; */ /* Port P1_6(CLK0) direction = output(Internal clock select) */
u0tbl = 0x00; /* UART0 transmit buffer register Low : data clear */
u0brg = 0x01; /* UART0 BRG : set 1(BRG divides the count sorce by 2(1+1) ) */
u0mr = 0x01; /* UART0 transmit/receive mode register : Clock synchronous serial I/O mode , Internal clock , 1stop bit , parity disabled */
u0c0 = 0x8a; /* UART0 transmit/receive control register0 : f32SIO , TxD0 pin is a pin of CMOS output , MSB first */
/* Transmit is output at falling edge of transfer clock and receive is input at rising edge */
u0c1 = 0x32; /* UART0 transmit/receive control register1 : transmit disabled , No data in U0TB , receive disabled , No data in U0RB , Transmission completed(TXEPT=1) , Enables continuous receive mode */
/* Interrupt */
s0tic = 0x00; /* UART0 transmit interrupt : Priority level-0(interrupt disable) , Interrupt request = clear */
s0ric = 0x00; /* UART0 recive interrupt : Priority level-0(interrupt disable) , Interrupt request = clear */
/* Interface RAM default set */
/* %%R8C2C2D-2009-LIN00%% */
sio_trx5_cont = 0x02+0x00+0x00+0x10;
/* %%R8C2C2D-2009-LIN01%% */
sio_trx5_brg = 0x01;
/* %%R8C2C2D-2009-LIN02%% */
sio_trx5_tx_auto_cnt = 0x07;
/* %%R8C2C2D-2009-LIN03%% */
sio_trx5_rx_auto_cnt = 0x07;
f_sio_trx5_sfr = 1; /* SFR initial setting flag : already set */
}
/************************************************************************************
Name :uart0_tra_int_func10
Parameters :-
Returns :-
Description :SI/O transmit interrupt
************************************************************************************/
void uart0_tra_int_func10(void){
asm("FSET I"); /* Interrupt enable */
if(sio_trx5_tx_cnt == 0){ /* SI/O automatic continuousness transmit buffer count 0? (Transmission end of the last data?) */
s0tic = 0x00; /* UART0 transmit interrupt : Priority level-0(interrupt disable) , Interrupt request = clear */
te_u0c1 = 0; /* UART0 transmit disabled */
sio_trx5_star = 0; /* Transmit stop */
/* Wait mode count reset */
c_sio_trx5_wait = 0x04; /* SI/O wait mode count reset (250usec * 4 = 1msec) */
}
else{
u0tbl = sio_trx5_tx_data[--sio_trx5_tx_cnt]; /* UART0 transmit buffer register Low : transmit data set(next data) */
}
}
/************************************************************************************
Name :uart0_rec_int_func14
Parameters :-
Returns :-
Description :SI/O receive interrupt
************************************************************************************/
void uart0_rec_int_func14(void){
unsigned short work;
unsigned char cnt;
asm("FSET I"); /* Interrupt enable */
work = u0rb; /* Read receive data(16bits) */
sio_trx5_rx_ena = 0; /* SI/O recive disabled (for communication synchronization) */
if((work & 0x1000) == 0){ /* No overrun error? */
sio_trx5_rx_data[sio_trx5_rx_cnt] = work & 0xff; /* Read receive data(8bits) */
if(sio_trx5_rx_cnt == 0){ /* SI/O automatic continuousness reception buffer counter = 0?(Transmission end of the last data?) */
s0ric = 0x00; /* UART0 recive interrupt : Priority level-0(interrupt disable) , Interrupt request = clear */
re_u0c1 = 0; /* Receive disabled */
te_u0c1 = 0; /* Transmit disabled */
sio_trx5_star = 0; /* Receive stop */
for(cnt=0;cnt<=7;cnt++){
sio_trx5_rx_auto_buf[cnt] = sio_trx5_rx_data[cnt]; /* Recive data(8bits) -> SI/O automatic continuousness reception buffer */
}
/* Wait mode count reset */
c_sio_trx5_wait = 0x04; /* SI/O wait mode count reset (250usec * 4 = 1msec) */
}
else{
--sio_trx5_rx_cnt; /* Count decrement */
}
}
else{
sio_trx5_rx_err = 1; /* SI/O receive error */
}
}
/************************************************************************************
Name :-
Parameters :-
Returns :-
Description :-
************************************************************************************/
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