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📄 xdp512regs.h

📁 关于XD256的应用实例,用于汽车电子开发之用
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/* XGate bit definitions */

#define XGE 0x80
#define XGFRZ 0x40
#define XGDBGM 0x20
#define XGDBG 0x10
#define XGSS 0x08
#define XGSWEIF 0x02
#define XGIE 0x01

#define RQST 0x80

/* SPI bit definitions */

#define SPIF 0x80
#define SPTEF 0x20

#define SPIE 0x80
#define SPTIE 0x20

/* CAN bit definitions */

#define RXF 0x01
#define CANE 0x80
#define RXFIE 0x01
#define INITAK 0x01

typedef struct {
                volatile uint Baud;			/* SCI BAUD rate register */
                volatile uchar CR1;			/* SCI Control Register #1 */
                volatile uchar CR2;			/* SCI Control Register #2 */
                volatile uchar SR1;			/* SCI Status Register #1 */
                volatile uchar SR2;			/* SCI Status Register #2 */
                volatile uchar DRH;			/* SCI Transmit/Receive Data Register (high byte) */
                volatile uchar DRL;			/* SCI Transmit/Receive Data Register (low byte) */
                
               } SCIRegs;

typedef struct {
                volatile uchar CR1;
                volatile uchar CR2;
                volatile uchar BR;
                volatile uchar SR;
                         uchar Reserved0x04;
                volatile uchar DR;
                         uchar Reserved0x06;
                         uchar Reserved0x07;
               } SPIRegs;

typedef struct {
                 volatile   uchar CTL0;			/* msCAN12 Module Control Register #0 */
                 volatile   uchar CTL1;			/* msCAN12 Module Control Register #1 */
                 volatile   uchar BTR0;			/* msCAN12 Bus Timing Register #0 */
                 volatile   uchar BTR1;			/* msCAN12 Bus Timing Register #1 */
                 volatile   uchar RFLG;			/* msCAN12 Receiver Flag Register */
                 volatile   uchar RIER;			/* msCAN12 Receiver Interrupt Enable Register */
                 volatile   uchar TFLG;			/* msCAN12 Transmitter Flag Register */
                 volatile   uchar TIER;			/*  */
                 volatile   uchar TARQ;			/*  */
                 volatile   uchar TAAK;			/*  */
                 volatile   uchar TBSEL;		/*  */
                 volatile   uchar IDAC;			/*  */
                            uchar Reserved0xXXc;
                            uchar Reserved0xXXd;
                 volatile   uchar RXERR;		/* msCAN12 Receive Error Counter */
                 volatile   uchar TXERR;		/* msCAN12 Transmit Error Counter */

                 volatile   uchar IDAR0;		/* msCAN12 Identifier Acceptance Register #0 */
                 volatile   uchar IDAR1;		/* msCAN12 Identifier Acceptance Register #1 */
                 volatile   uchar IDAR2;		/* msCAN12 Identifier Acceptance Register #2 */
                 volatile   uchar IDAR3;		/* msCAN12 Identifier Acceptance Register #3 */
                 volatile   uchar IDMR0;		/* msCAN12 Identifier Mask Register #0 */
                 volatile   uchar IDMR1;		/* msCAN12 Identifier Mask Register #1 */
                 volatile   uchar IDMR2;		/* msCAN12 Identifier Mask Register #2 */
                 volatile   uchar IDMR3;		/* msCAN12 Identifier Mask Register #3 */
                 volatile   uchar IDAR4;		/* msCAN12 Identifier Acceptance Register #4 */
                 volatile   uchar IDAR5;		/* msCAN12 Identifier Acceptance Register #5 */
                 volatile   uchar IDAR6;		/* msCAN12 Identifier Acceptance Register #6 */
                 volatile   uchar IDAR7;		/* msCAN12 Identifier Acceptance Register #7 */
                 volatile   uchar IDMR4;		/* msCAN12 Identifier Mask Register #4 */
                 volatile   uchar IDMR5;		/* msCAN12 Identifier Mask Register #5 */
                 volatile   uchar IDMR6;		/* msCAN12 Identifier Mask Register #6 */
                 volatile   uchar IDMR7;		/* msCAN12 Identifier Mask Register #7 */

                 volatile   uchar RxFG[16];		/* Foreground Receive Buffer */

                 volatile   uchar TxFG[16];		/* Foreground Transmit Buffer */

               } CANRegs;


typedef struct {
                 volatile	uchar PORTA;		/* port A */
                 volatile	uchar PORTB;		/* port B */
                 volatile   uchar DDRA;			/* data direction port A */
                 volatile   uchar DDRB;			/* data direction port B */
                 volatile   uchar PORTC;
                 volatile   uchar PORTD;
                 volatile   uchar DDRC;
                 volatile   uchar DDRD;
                 volatile	uchar PORTE;		/* port E */
                 volatile   uchar DDRE;			/* data direction port E */
                 volatile   uchar EIFCTL;
                 volatile   uchar MODE;			/* mode register */
                 volatile   uchar PUCR;			/* pull-up control register */
                 volatile   uchar RDRIV;		/* reduced drive of I/O lines */
                 volatile   uchar Reserved0x0e;	/*  */
                 volatile   uchar Reserved0x0f;


                 volatile   uchar GPAGE;		/* Global Page register */
                 volatile   uchar Reserved0x11;	/* IO mapping register */
                 volatile   uchar DIRECT;		/* Direct page mapping register */
                 volatile   uchar MISC;			/* mapping control register */
                 volatile   uchar Reserved0x14;
                 volatile   uchar Reserved0x15;
                 volatile   uchar RPAGE;		/* RAM Paging register */
                 volatile   uchar EPAGE;		/* EEPROM paging register */
                            uchar Reserved0x18;
                            uchar Reserved0x19;
                            uchar PARTIDH;		/* Part ID High byte */
                            uchar PARTIDL;		/* Part ID Low byte */
                 volatile   uchar Reserved0x1c;
                 volatile   uchar Reserved0x1d;
                 volatile   uchar IRQCR;		/* interrupt control */
                 volatile   uchar Reserved0x1f;


                 volatile   uchar DBGC1;		/* Debug control register 1 */
                 volatile   uchar DBGSR;		/* Debug status register */
                 volatile   uchar DBGTCR;		/* Debug trigger control register */
                 volatile   uchar DBGC2;		/* Debug control register 2 */
                 volatile   uint  DBGTB;		/* Debug trace buffer */
                 volatile   uchar DBGCNT;		/* Debug trace buffer count */
                 volatile   uchar DBGSCR;		/* Debug state control register */
                            
                 volatile   uchar DBGXCTL;		/* Debug Comparitor Control Register 0 */
                 volatile   uchar DBGXAH;		/* Debug Comparitor address high */
                 volatile   uchar DBGXAM;		/* Debug Comparitor address mid */
                 volatile   uchar DBGXAL;		/* Debug Comparitor address low */
                 volatile   uchar DBGXDH;		/* Debug Comparitor data high */
                 volatile   uchar DBGXDL;		/* Debug Comparitor data low */
                 volatile   uchar DBGXDHM;		/* Debug Comparitor data mask high */
                 volatile   uchar DBGXDLM;		/* Debug Comparitor data mask low */

                 volatile   uchar PPAGE;		/* PPAGE memory expansion register */
                            uchar Reserved0x31;
                 volatile   uchar PORTK;		/*  */
                 volatile   uchar DDRK;			/*  */
                 volatile   uchar SYNR;			/*  */
                 volatile   uchar REFDV;		/*  */
                 volatile   uchar CTFLG;		/*  */
                 volatile   uchar CRGFLG;		/*  */
                 volatile   uchar CRGINT;		/*  */
                 volatile   uchar CLKSEL;		/*  */
                 volatile   uchar PLLCTL;		/*  */
                 volatile   uchar RTICTL;		/*  */
                 volatile   uchar COPCTL;		/*  */
                 volatile   uchar FORBYP;		/*  */
                 volatile   uchar CTCTL;		/*  */
                 volatile   uchar ARMCOP;		/*  */



                 volatile   uchar TIOS;			/* time select */
                 volatile   uchar CFORC;		/* compare force */
                 volatile   uchar OC7M;			/* oc7 mask */
                 volatile   uchar OC7D;			/* oc7 data */
                 volatile	uint  TCNT;			/* timer counter */
                 volatile   uchar TSCR1;		/* timer system control */
                 volatile   uchar TTOV;			/* timer Toggle On Overflow */
                 volatile   uchar TCTL1;		/* timer control 1 */
                 volatile   uchar TCTL2;		/* timer control 2 */
                 volatile   uchar TCTL3;		/* timer control 3 */
                 volatile   uchar TCTL4;		/* timer control 4 */
                 volatile   uchar TIE;			/* timer interrupt mask 1 */
                 volatile   uchar TSCR2;		/* timer interrupt mask 2 */
                 volatile	uchar TFLG1;		/* timer interrupt flag 1 */
                 volatile	uchar TFLG2;		/* timer interrupt flag 2 */

                 volatile	uint  TC0;			/* timer capture/compare 0 */
                 volatile	uint  TC1;			/* timer capture/compare 1 */
                 volatile	uint  TC2;			/* timer capture/compare 2 */
                 volatile	uint  TC3;			/* timer capture/compare 3 */
                 volatile	uint  TC4;			/* timer capture/compare 4 */
                 volatile	uint  TC5;			/* timer capture/compare 5 */
                 volatile	uint  TC6;			/* timer capture/compare 6 */
                 volatile	uint  TC7;			/* timer capture/compare 7 */

                 volatile   uchar PACTL;		/* pulse accumulator control */
                 volatile   uchar PAFLG;		/* pulse accumulator flag */
                 volatile   uchar PACN3;		/* 8-bit pulse accumulator #3 count */
                 volatile   uchar PACN2;		/* 8-bit pulse accumulator #2 count */
                 volatile   uchar PACN1;		/* 8-bit pulse accumulator #1 count */
                 volatile   uchar PACN0;		/* 8-bit pulse accumulator #0 count */
                 volatile   uchar MCCTL;		/* 16-bit Modulus Down-counter control register */
                 volatile   uchar MCFLG;		/* 16-bit Modulus Down-counter flaf register */
                 volatile   uchar ICPACR;		/* Input Control Pulse Accumulators Control Register */
                 volatile   uchar DLYCT;		/* Input Capture Delay Counter control register */
                 volatile   uchar ICOVW;		/* Input Capture Overwrite control register */
                 volatile   uchar ICSYS;		/* Input Capture System Control Register */
                            uchar Reserved0x6c;
                 volatile   uchar TIMTST;		/* timer test register */
                 volatile   uchar PTPSR;
                 volatile   uchar PTMCPSR;

                 volatile   uchar PBCTL;		/* 16-bit pulse accumulator B Control Register */
                 volatile   uchar PBFLG;		/* 16-bit pulse accumulator B Flag Register */
                 volatile   uchar PA3H;			/* 8-bit pulse accumulator #3 Holding Register */
                 volatile   uchar PA2H;			/* 8-bit pulse accumulator #2 Holding Register */
                 volatile   uchar PA1H;			/* 8-bit pulse accumulator #1 Holding Register */
                 volatile   uchar PA0H;			/* 8-bit pulse accumulator #0 Holding Register */
                 volatile   uint  MCCNT;		/* Modulus Down-Counter Count Register */
                 volatile   uint  TCOH;			/* Input Capture Holding register #0 */
                 volatile   uint  TC1H;			/* Input Capture Holding register #1 */
                 volatile   uint  TC2H;			/* Input Capture Holding register #2 */

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