📄 adc.lst
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195 1
196 1 /// Configuration of Result Control Register 1
197 1 /// - the data reduction filter is disabled
198 1 /// - the event interrupt is disabled
199 1 /// - the wait-for-read mode is disabled
200 1 /// - the VF unchaned by read access to RESRxH/RESRAxH
201 1
202 1 ADC_RCR1 = 0x00; // load result control register 1
203 1
204 1 /// Configuration of Result Control Register 2
205 1 /// - the data reduction filter is disabled
206 1 /// - the event interrupt is disabled
207 1 /// - the wait-for-read mode is disabled
208 1 /// - the VF unchaned by read access to RESRxH/RESRAxH
209 1
210 1 ADC_RCR2 = 0x00; // load result control register 2
211 1
212 1 /// Configuration of Result Control Register 3
213 1 /// - the data reduction filter is disabled
214 1 /// - the event interrupt is disabled
215 1 /// - the wait-for-read mode is disabled
216 1 /// - the VF unchaned by read access to RESRxH/RESRAxH
217 1
218 1 ADC_RCR3 = 0x00; // load result control register 3
219 1
220 1 SFR_PAGE(_ad5, noSST); // switch to page 5
221 1
222 1 /// -----------------------------------------------------------------------
223 1 /// Configuration of Channel Interrupt Node Pointer Register:
224 1 /// -----------------------------------------------------------------------
225 1 /// - the SR 0 line become activated if channel 0 interrupt is generated
226 1 /// - the SR 0 line become activated if channel 1 interrupt is generated
227 1 /// - the SR 0 line become activated if channel 2 interrupt is generated
228 1 /// - the SR 0 line become activated if channel 3 interrupt is generated
229 1 /// - the SR 0 line become activated if channel 4 interrupt is generated
230 1 /// - the SR 0 line become activated if channel 5 interrupt is generated
231 1 /// - the SR 0 line become activated if channel 6 interrupt is generated
232 1 /// - the SR 0 line become activated if channel 7 interrupt is generated
233 1
234 1 ADC_CHINPR = 0x00; // load channel interrupt node pointer
235 1 // register
236 1
237 1 /// -----------------------------------------------------------------------
238 1 /// Configuration of Event Interrupt Node Pointer Registers:
239 1 /// -----------------------------------------------------------------------
240 1 /// - the SR 0 line become activated if the event 0 interrupt is generated
241 1 /// - the SR 0 line become activated if the event 1 interrupt is generated
C51 COMPILER V8.04b ADC 04/26/2008 19:04:54 PAGE 5
242 1 /// - the SR 0 line become activated if the event 4 interrupt is generated
243 1 /// - the SR 0 line become activated if the event 5 interrupt is generated
244 1 /// - the SR 0 line become activated if the event 6 interrupt is generated
245 1 /// - the SR 0 line become activated if the event 7 interrupt is generated
246 1
247 1 ADC_EVINPR = 0x00; // load event interrupt set flag register
248 1
249 1 SFR_PAGE(_ad0, noSST); // switch to page 0
250 1
251 1 /// -----------------------------------------------------------------------
252 1 /// Configuration of Limit Check Boundary:
253 1 /// -----------------------------------------------------------------------
254 1
255 1 ADC_LCBR = 0xB7; // load limit check boundary register
256 1
257 1 /// -----------------------------------------------------------------------
258 1 /// Configuration of External Trigger Control:
259 1 /// -----------------------------------------------------------------------
260 1 /// - the trigger input ETR00 is selected for Source 0
261 1 /// - the trigger input ETR10 is selected for Source 1
262 1 /// - the synchronizing stage is not in external trigger input REQTR0 path
263 1 /// - the synchronizing stage is not in external trigger input REQTR1 path
264 1
265 1 ADC_ETRCR = 0x00; // load external trigger control register
266 1
267 1 SFR_PAGE(_ad6, noSST); // switch to page 6
268 1
269 1 /// -----------------------------------------------------------------------
270 1 /// Configuration of Conversion Queue Mode Register:
271 1 /// -----------------------------------------------------------------------
272 1 /// - the gating line is permanently 0
273 1 /// - the external trigger is disabled
274 1 /// - the trigger mode 0 is selected
275 1
276 1 ADC_QMR0 = 0x00; // load queue mode register
277 1
278 1 /// -----------------------------------------------------------------------
279 1 /// Configuration of Conversion Request Mode Registers:
280 1 /// -----------------------------------------------------------------------
281 1 /// - the gating line is permanently 1
282 1 /// - the external trigger is disabled
283 1 /// - the source interrupt is disabled
284 1 /// - the autoscan functionality is enabled
285 1
286 1 ADC_CRMR1 = 0x11; // load conversion request mode register 1
287 1
288 1 SFR_PAGE(_ad0, noSST); // switch to page 0
289 1
290 1 ADC_GLOBCTR |= 0x80; // turn on Analog part
291 1
292 1 /// - ADC -Interrupt enable bit is set in SHINT_vInit() function
293 1
294 1 // USER CODE BEGIN (ADC_Init,3)
295 1
296 1 // USER CODE END
297 1
298 1 } // End of function ADC_vInit
299
300
301 //****************************************************************************
302 // @Function void ADC_vStartParReqChNum(ubyte ubChannelNum)
303 //
C51 COMPILER V8.04b ADC 04/26/2008 19:04:54 PAGE 6
304 //----------------------------------------------------------------------------
305 // @Description This function strarts conversion request of analog
306 // channel.The possible values for the request channels are:
307 // Bit 4 = 1 -> analog channel 4 is requested for
308 // conversion
309 // Bit 5 = 1 -> analog channel 5 is requested for
310 // conversion
311 // Bit 6 = 1 -> analog channel 6 is requested for
312 // conversion
313 // Bit 7 = 1 -> analog channel 7 is requested for
314 // conversion
315 //
316 //----------------------------------------------------------------------------
317 // @Returnvalue None
318 //
319 //----------------------------------------------------------------------------
320 // @Parameters ubChannelNum:
321 // Name of the Valid Flag Register
322 //
323 //----------------------------------------------------------------------------
324 // @Date 2008-3-22
325 //
326 //****************************************************************************
327
328 void ADC_vStartParReqChNum(ubyte ubChannelNum)
329 {
330 1
331 1 SFR_PAGE(_ad6, SST1); // switch to page 6
332 1
333 1 ADC_CRPR1 |= ubChannelNum ; // requested channel number
334 1
335 1 SFR_PAGE(_ad0, RST1); // restore the old ADC page
336 1
337 1 } // End of function ADC_vStartParReqChNum
338
339
340 //****************************************************************************
341 // @Function uword ADC_uwGetResultData0(void)
342 //
343 //----------------------------------------------------------------------------
344 // @Description This function reads the 8- or 10-bit conversion results
345 // from result register 0
346 //
347 //----------------------------------------------------------------------------
348 // @Returnvalue Conversion Result
349 //
350 //----------------------------------------------------------------------------
351 // @Parameters None
352 //
353 //----------------------------------------------------------------------------
354 // @Date 2008-3-22
355 //
356 //****************************************************************************
357
358 uword ADC_uwGetResultData0(void)
359 {
360 1 uword uwResult = 0;
361 1
362 1 SFR_PAGE(_ad2, SST1); // switch to page 2
363 1
364 1 if ( ADC_RESR0L & 0x10 ) // if Result Register0 contains valid data
365 1 {
C51 COMPILER V8.04b ADC 04/26/2008 19:04:54 PAGE 7
366 2 // 8-bit conversion (without accumulation)
367 2 uwResult = ADC_RESR0H; // Result Register0 High
368 2 }
369 1
370 1 SFR_PAGE(_ad0, RST1); // restore the old ADC page
371 1
372 1 return(uwResult);
373 1 } // End of function ADC_uwGetResultData0
374
375
376
377
378 // USER CODE BEGIN (ADC_General,10)
379
380 // USER CODE END
381
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 85 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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