📄 start_v2.lst
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646 ; 1024*KB or 1*MB (gives RGSZ1 = 8)
647 ; 2048*KB or 2*MB (gives RGSZ1 = 9)
648 ; 4096*KB or 4*MB (gives RGSZ1 = 10)
A166 MACRO ASSEMBLER START_V2 12/10/2006 17:29:06 PAGE 11
649 ; 8192*KB or 8*MB (gives RGSZ1 = 11)
650 ; (RGSZ1 = 12 .. 15 reserved)
651 ;</h>
652 ;
653 ; <h>Definitions for Function Configuration Register FCONCS1
654 ; =======================================================
655 ;
656 ; <q> ENCS1: Enable Chip Select (FCONCS1.0)
0001 657 _ENCS1 EQU 1 ; 0 = Chip Select 0 disabled
658 ; 1 = Chip Select 0 enabled
659 ;
660 ; <q> RDYEN1: Ready Enable (FCONCS1.1)
0000 661 _RDYEN1 EQU 0 ; 0 = Access time controlled by TCONCS1.PHE1
662 ; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
663 ;
664 ; <o> RDYMOD1: Ready Mode (FCONCS1.2)
665 ; <0=> Asynchronous <1=> Synchronous
0000 666 _RDYMOD1 EQU 0 ; 0 = Asynchronous READY
667 ; 1 = Synchronous READY
668 ;
669 ; <o> BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
670 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
671 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 672 _BTYP1 EQU 2 ; 0 = 8 bit Demultiplexed bus
673 ; 1 = 8 bit Multiplexed bus
674 ; 2 = 16 bit Demultiplexed bus
675 ; 3 = 16 bit Multiplexed bus
676 ;</h>
677 ;
678 ; <h>TCONCS1: Definitions for the Timing Configuration register
679 ; ==========================================================
680 ;
681 ; <o>PHA1: Phase A clock cycles (TCONCS1.0 .. TCONCS1.1) <0-3>
0000 682 _PHA1 EQU 0 ; 0 = 0 clock cycles
683 ; : = :
684 ; 3 = 3 clock cycles
685 ;
686 ; <o>PHB1: Phase B clock cycles (TCONCS1.2) <1-2> <#-1>
0000 687 _PHB1 EQU 0 ; 0 = 1 clock cycle
688 ; 1 = 2 clock cycles
689 ;
690 ; <o>PHC1: Phase C clock cycles (TCONCS1.3 .. TCONCS1.4) <0-3>
0000 691 _PHC1 EQU 0 ; 0 = 0 clock cycles
692 ; : = :
693 ; 3 = 3 clock cycles
694 ;
695 ; <o>PHD1: Phase D clock cycles (TCONCS1.5) <0-1>
0000 696 _PHD1 EQU 0 ; 0 = 0 clock cycles
697 ; 1 = 1 clock cycle
698 ;
699 ; <o> PHE1: Phase E clock cycles (TCONCS1.6 .. TCONCS1.10) <1-32> <#-1>
0008 700 _PHE1 EQU 8 ; 0 = 1 clock cycle
701 ; : = :
702 ; 31 = 32 clock cycles
703 ;
704 ; <o>RDPHF1: Phase F read clock cycles (TCONCS1.11 .. TCONCS1.12) <0-3>
0000 705 _RDPHF1 EQU 0 ; 0 = 0 clock cycles
706 ; : = :
707 ; 3 = 3 clock cycles
708 ;
709 ; <o>WRPHF1: Phase F write clock cycles (TCONCS1.13 .. TCONCS1.14) <0-3>
0003 710 _WRPHF1 EQU 3 ; 0 = 0 clock cycles
711 ; : = :
712 ; 3 = 3 clock cycles
713 ;</h> </e>
714 ;
A166 MACRO ASSEMBLER START_V2 12/10/2006 17:29:06 PAGE 12
715 ;<e>Configure External Bus Behaviour for CS2 Area
716 ; =============================================
717 ;
718 ; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
719 $SET (CONFIG_CS2 = 0)
720 ;
721 ; <h>Definitions for Address Select register ADDRSEL2
722 ; ===================================================
723 ; <o> CS2 Start Address <0x0-0xFFFFFF:0x1000>
00200000 724 _ADDR2 EQU 0x200000 ; Set CS2# Start Address (default 100000H)
725
726 ; <o> CS2 Size in KB
727 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
728 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
729 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 730 _SIZE2 EQU 1024*KB ; Set CS2# Size (default 1024*KB = 1*MB)
731 ; possible values for _SIZE2 are:
732 ; 4*KB (gives RGSZ2 = 0)
733 ; 8*KB (gives RGSZ2 = 1)
734 ; 16*KB (gives RGSZ2 = 2)
735 ; 32*KB (gives RGSZ2 = 3)
736 ; 64*KB (gives RGSZ2 = 4)
737 ; 128*KB (gives RGSZ2 = 5)
738 ; 256*KB (gives RGSZ2 = 6)
739 ; 512*KB (gives RGSZ2 = 7)
740 ; 1024*KB or 1*MB (gives RGSZ2 = 8)
741 ; 2048*KB or 2*MB (gives RGSZ2 = 9)
742 ; 4096*KB or 4*MB (gives RGSZ2 = 10)
743 ; 8192*KB or 8*MB (gives RGSZ2 = 11)
744 ; (RGSZ2 = 12 .. 15 reserved)
745 ;</h>
746 ;
747 ; <h>Definitions for Function Configuration Register FCONCS2
748 ; =======================================================
749 ;
750 ; <q> ENCS2: Enable Chip Select (FCONCS2.0)
0001 751 _ENCS2 EQU 1 ; 0 = Chip Select 0 disabled
752 ; 1 = Chip Select 0 enabled
753 ;
754 ; <q> RDYEN2: Ready Enable (FCONCS2.1)
0000 755 _RDYEN2 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE1
756 ; 1 = Access time cont. by TCONCS2.PHE1 and READY signal
757 ;
758 ; <o> RDYMOD2: Ready Mode (FCONCS2.2)
759 ; <0=> Asynchronous <1=> Synchronous
0000 760 _RDYMOD2 EQU 0 ; 0 = Asynchronous READY
761 ; 1 = Synchronous READY
762 ;
763 ; <o> BTYP2: Bus Type Selection (FCONCS2.4 .. FCONCS2.5)
764 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
765 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 766 _BTYP2 EQU 2 ; 0 = 8 bit Demultiplexed bus
767 ; 1 = 8 bit Multiplexed bus
768 ; 2 = 16 bit Demultiplexed bus
769 ; 3 = 16 bit Multiplexed bus
770 ;</h>
771 ;
772 ; <h>TCONCS2: Definitions for the Timing Configuration register
773 ; ==========================================================
774 ;
775 ; <o>PHA2: Phase A clock cycle (TCONCS2.0 .. TCONCS2.1) <0-3>
0000 776 _PHA2 EQU 0 ; 0 = 0 clock cycles
777 ; : = :
778 ; 3 = 3 clock cycles
779 ;
780 ; <o>PHB2: Phase B clock cycle (TCONCS2.2) <1-2> <#-1>
A166 MACRO ASSEMBLER START_V2 12/10/2006 17:29:06 PAGE 13
0000 781 _PHB2 EQU 0 ; 0 = 1 clock cycle
782 ; 1 = 2 clock cycles
783 ;
784 ; <o>PHC2: Phase C clock cycle (TCONCS2.3 .. TCONCS2.4) <0-3>
0000 785 _PHC2 EQU 0 ; 0 = 0 clock cycles
786 ; : = :
787 ; 3 = 3 clock cycles
788 ;
789 ; <o>PHD2: Phase D clock cycle (TCONCS2.5) <0-1>
0000 790 _PHD2 EQU 0 ; 0 = 0 clock cycles
791 ; 1 = 1 clock cycle
792 ;
793 ; <o> PHE2: Phase E clock cycle (TCONCS2.6 .. TCONCS2.10) <1-32> <#-1>
0008 794 _PHE2 EQU 8 ; 0 = 1 clock cycle
795 ; : = :
796 ; 31 = 32 clock cycles
797 ;
798 ; <o>RDPHF2: Phase F read clock cycle (TCONCS2.11 .. TCONCS2.12) <0-3>
0000 799 _RDPHF2 EQU 0 ; 0 = 0 clock cycles
800 ; : = :
801 ; 3 = 3 clock cycles
802 ;
803 ; <o>WRPHF2: Phase F write clock cycle (TCONCS2.13 .. TCONCS2.14) <0-3>
0003 804 _WRPHF2 EQU 3 ; 0 = 0 clock cycles
805 ; : = :
806 ; 3 = 3 clock cycles
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