📄 start_v2.lst
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0008 481 _CSPEN EQU 8 ; 0 = No CS pins enabled
482 ; 1 = One CS (CS0) pin enabled
483 ; : = :
484 ; 8 = Eight CS (CS0 .. CS7) pins enabled
485 ; 9 - 15 = reserved
486 ; Note: the number of available CS pins depends on the chip used
487 ;
488 ; <q> ARBEN: Enable Bus Arbitration Pins (EBCMOD0.8)
0000 489 _ARBEN EQU 0 ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
490 ; 1 = HOLD, HLDA and BREQ pins act normally
491 ;
492 ; <o> SLAVE: SLAVE mode enable (EBCMOD0.9)
493 ; <0=> Master Mode <1=> Slave Mode
0000 494 _SLAVE EQU 0 ; 0 = Bus arbiter acts in master mode
495 ; 1 = Bus arbiter acts in slave mode
496 ;
497 ; <q> EBCDIS: Disable EBC pins (EBCMOD0.10)
0000 498 _EBCDIS EQU 0 ; 0 = EBC is using the pins for external bus
499 ; 1 = EBC off (pins to be used as GPIO if implemented)
500 ;
501 ; <o> WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
502 ; <0=> WR and BHE <1=> WRL and WRH
0000 503 _WRCFG EQU 0 ; 0 = Pins act as WR and BHE
504 ; 1 = Pins act as WRL and WRH
505 ;
506 ; <q> BYTDIS: Disable BHE pin (EBCMOD0.12)
0000 507 _BYTDIS EQU 0 ; 0 = BHE enabled
508 ; 1 = BHE disabled (GPIO function if implemented)
509 ;
510 ; <q> ALEDIS: Disable ALE pin (EBCMOD0.13)
0000 511 _ALEDIS EQU 0 ; 0 = ALE pin enabled
512 ; 1 = ALE pin disabled (GPIO function if implemented)
513 ;
514 ; <q> RDYDIS: Disable READY pin (EBCMOD0.14)
0000 515 _RDYDIS EQU 0 ; 0 = READY enabled
516 ; 1 = READY disabled (GPIO function if implemented)
A166 MACRO ASSEMBLER START_V2 12/10/2006 17:29:06 PAGE 9
517 ;
518 ; <o> RDYPOL: READY pin polarity (EBCMOD0.15)
519 ; <0=> Active Low <1=> Active High
0000 520 _RDYPOL EQU 0 ; 0 = READY pin is active low
521 ; 1 = READY pin is active high
522 ;
523 ;</h>
524 ;
525 ; <h>Definitions for EBC Mode 1 register EBCMOD1
526 ; ==============================================
527 ;
528 ; <o> APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD1.3) <0-15>
0000 529 _APDIS EQU 0 ; 0 = Address bus pins 15-1 of PORT1 enabled
530 ; 1 = Pin A15 disabled, A14-1 enabled
531 ; 2 = Pin A15-A14 disabled, A13-1 enabled
532 ; ...
533 ; 15 = Pins A15-A1 disabled
534 ;
535 ; <q> A0PDIS: Address Bit 0 Pin Disable (EBCMOD1.4)
0000 536 _A0PDIS EQU 0 ; 0 = Address bus pin 0 of PORT1 enabled
537 ; 1 = Address bus pin 0 of PORT1 enabled
538 ;
539 ; <q> ALPDIS: Address Low Pins Disable (EBCMOD1.5)
0000 540 _ALPDIS EQU 0 ; 0 = Address bus pin 7-0 generally enabled
541 ; 1 = Address bus pin 7-0 of PORT1 disabled
542 ;
543 ; <q> DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
0000 544 _DHPDIS EQU 0 ; 0 = Data bus pins 15-8 of PORT0 enabled
545 ; 1 = Data bus pins 15-8 disabled (used as GPIO)
546 ;
547 ; <q> WRPDIS: WR/WRL Pin Disable (EBCMOD1.7)
0000 548 _WRPDIS EQU 0 ; 0 = WR/WRL pin of Port P20 enabled
549 ; 1 = WR/WRL pin of Port P20 disabled
550 ;
551 ;</h></e>
552 ;
553 ; <e> Configure External Bus Behaviour for CS0 area
554 ; =================================================
555 ;
556 ; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
557 $SET (CONFIG_CS0 = 1)
558 ;
559 ; <h>Definitions for Function Configuration Register FCONCS0
560 ; =======================================================
561 ;
562 ; <q> ENCS0: Enable Chip Select (FCONCS0.0)
0001 563 _ENCS0 EQU 1 ; 0 = Chip Select 0 disabled
564 ; 1 = Chip Select 0 enabled
565 ;
566 ; <q> RDYEN0: Ready Enable (FCONCS0.1)
0000 567 _RDYEN0 EQU 0 ; 0 = Access time controlled by TCONCS0.PHE0
568 ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
569 ;
570 ; <o> RDYMOD0: Ready Mode (FCONCS0.2)
571 ; <0=> Asynchronous <1=> Synchronous
0000 572 _RDYMOD0 EQU 0 ; 0 = Asynchronous READY
573 ; 1 = Synchronous READY
574 ;
575 ; <o> BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
576 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
577 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 578 _BTYP0 EQU 2 ; 0 = 8 bit Demultiplexed bus
579 ; 1 = 8 bit Multiplexed bus
580 ; 2 = 16 bit Demultiplexed bus
581 ; 3 = 16 bit Multiplexed bus
582 ; </h>
A166 MACRO ASSEMBLER START_V2 12/10/2006 17:29:06 PAGE 10
583 ;
584 ; <h> TCONCS0: Definitions for the Timing Configuration register
585 ; ==============================================================
586 ;
587 ; <o> PHA0: Phase A clock cycles (TCONCS0.0 .. TCONCS0.1) <0-3>
0000 588 _PHA0 EQU 0 ; 0 = 0 clock cycles
589 ; : = :
590 ; 3 = 3 clock cycles
591 ;
592 ; <o> PHB0: Phase B clock cycles (TCONCS0.2) <1-2> <#-1>
0000 593 _PHB0 EQU 0 ; 0 = 1 clock cycle
594 ; 1 = 2 clock cycles
595 ;
596 ; <o> PHC0: Phase C clock cycles (TCONCS0.3 .. TCONCS0.4) <0-3>
0000 597 _PHC0 EQU 0 ; 0 = 0 clock cycles
598 ; : = :
599 ; 3 = 3 clock cycles
600 ;
601 ; <o> PHD0: Phase D clock cycle (TCONCS0.5) <0-1>
0000 602 _PHD0 EQU 0 ; 0 = 0 clock cycles
603 ; 1 = 1 clock cycle
604 ;
605 ; <o> PHE0: Phase E clock cycles (TCONCS0.6 .. TCONCS0.10) <1-32> <#-1>
0008 606 _PHE0 EQU 8 ; 0 = 1 clock cycle
607 ; : = :
608 ; 31 = 32 clock cycles
609 ;
610 ; <o> RDPHF0: Phase F read clock cycles (TCONCS0.11 .. TCONCS0.12) <0-3>
0000 611 _RDPHF0 EQU 0 ; 0 = 0 clock cycles
612 ; : = :
613 ; 3 = 3 clock cycles
614 ;
615 ; <o> WRPHF0: Phase F write clock cycles (TCONCS0.13 .. TCONCS0.14) <0-3>
0003 616 _WRPHF0 EQU 3 ; 0 = 0 clock cycles
617 ; : = :
618 ; 3 = 3 clock cycles
619 ;</h> </e>
620 ;
621 ; <e> Configure External Bus Behaviour for CS1 Area
622 ; =================================================
623 ;
624 ; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
625 $SET (CONFIG_CS1 = 0)
626 ;
627 ; <h>Definitions for Address Select register ADDRSEL1
628 ; ===================================================
629 ; <o> CS1 Start Address <0x0-0xFFFFFF:0x1000>
00100000 630 _ADDR1 EQU 0x100000 ; Set CS1# Start Address (default 100000H)
631
632 ; <o> CS1 Size in KB
633 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
634 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
635 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 636 _SIZE1 EQU 1024*KB ; Set CS1# Size (default 1024*KB = 1*MB)
637 ; possible values for _SIZE1 are:
638 ; 4*KB (gives RGSZ1 = 0)
639 ; 8*KB (gives RGSZ1 = 1)
640 ; 16*KB (gives RGSZ1 = 2)
641 ; 32*KB (gives RGSZ1 = 3)
642 ; 64*KB (gives RGSZ1 = 4)
643 ; 128*KB (gives RGSZ1 = 5)
644 ; 256*KB (gives RGSZ1 = 6)
645 ; 512*KB (gives RGSZ1 = 7)
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