📄 start_v2.lst
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322 ;<q> Disable Synchronus Serial Cnl1 SSC1
A166 MACRO ASSEMBLER START_V2 12/10/2006 17:29:06 PAGE 6
0000 323 SSC1DIS EQU 0 ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15)
324 ;
325 ;</e>
326 ;</h>
327 ; <e> Definitions for Reset Configuration Register RSTCON
328 ; =======================================================
329 ;
330 ; INIT_RSTCON: Init RSTCON register
331 ; --- Set INIT_RSTCON = 0 to initilize the RSTCON register
332 $SET (INIT_RSTCON = 1)
333 ;
334 ; <o> RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
335 ; <0=> 2 CPU clocks <1=> 4 CPU clocks <2=> 8 CPU clocks <3=> 16 CPU clocks
336 ; <4=> 32 CPU clocks <5=> 64 CPU clocks <6=> 128 CPU clocks <7=> 256 CPU clocks
0000 337 _RSTLEN EQU 0 ; 0 = 2 t_CPU clocks (default)
338 ; 1 = 4 t_CPU clocks
339 ; 2 = 8 t_CPU clocks
340 ; 3 = 16 t_CPU clocks
341 ; 4 = 32 t_CPU clocks
342 ; 5 = 64 t_CPU clocks
343 ; 6 = 128 t_CPU clocks
344 ; 7 = 256 t_CPU clocks
345 ;
346 ; <o> RORMV: RSTOUT# Remove Control (RSTCON.4)
347 ; <0=> RSTOUT delivers RSTOUT# signal <1=> RSTOUT pin operates as GPIO
0000 348 _RORMV EQU 0 ; 0 = RSTOUT delivers RSTOUT# signal
349 ; 1 = RSTOUT pin operates as GPIO
350 ;
351 ; <o> ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
352 ; <0=>RSTOUT deactivated by user software <1=>RSTOUT deactivated after reset
0000 353 _ROCOFF EQU 0 ; 0 = RSTOUT is deactivated by user software
354 ; 1 = RSTOUT is deactivated at end of reset
355 ;
356 ; <o> ROCON: RSTOUT# Control Switch Off (RSTCON.6)
357 ; <0=> RSTOUT active on any reset <1=> RSTOUT active on hardware reset
0000 358 _ROCON EQU 0 ; 0 = RSTOUT is activated upon any reset
359 ; 1 = RSTOUT is only activated upon a hardware reset
360 ;
361 ; <q> RODIS: RSTOUT# Disable Control (RSTCON.7) <0-1>
0000 362 _RODIS EQU 0 ; 0 = RSTOUT is controlled by other mechanism
363 ; 1 = RSTOUT is deactivated
364 ;
365 ;</e>
366 ;
367 ;
368 ; <e> Definitions for PLL Control Register PLLCON
369 ; ===============================================
370 ;
371 ; INIT_PLLCON: Init PLLCON register
372 ; --- Set INIT_PLLCON = 0 to initilize the PLLCON register
373 $SET (INIT_PLLCON = 1)
374 ;
375 ; <o> PLLODIV: PLL Output Divider (PLLCON.0 .. PLLCON.3) <0-14>
0004 376 _PLLODIV EQU 4 ; 0 .. 14 Fpll = Fvco / (PLLODIV+1)
377 ; 15 = reserved
378 ;
379 ; <o> PLLIDIV: PLL Input Divider (PLLCON.4 .. PLLCON.5) <0-3>
380 ; <i> Fin = Fosc / (PLLIDIV+1)
0000 381 _PLLIDIV EQU 0 ; 0 .. 3 Fin = Fosc / (PLLIDIV+1)
382 ;
383 ; <o> PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
384 ; <0=> Ouput:100-150MHz / Base:20-80MHz <1=> Ouput:150-200MHz / Base:40-130MHz
385 ; <2=> Ouput:200-250MHz / Base:60-180MHz <3=> (250...300 MHz) Reserved
0002 386 _PLLVB EQU 2 ; ValueVCO output frequency Base frequency
387 ; 0 = 100...150 MHz 20...80 MHz
388 ; 1 = 150...200 MHz 40...130 MHz
A166 MACRO ASSEMBLER START_V2 12/10/2006 17:29:06 PAGE 7
389 ; 2 = 200...250 MHz [def.] 60...180 MHz
390 ; 3 = (250...300 MHz) Reserved
391 ;
392 ; <o> PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12) <6-31>
393 ; <i> Fvco = Fin * (PLLMUL+1)
0018 394 _PLLMUL EQU 24 ; 7 .. 31 Fvco = Fin * (PLLMUL+1)
395 ; 0 .. 6 = reserved
396 ;
397 ; <o> PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
398 ; <0=> Bypass PLL clock mult., the VCO is off <1=> Bypass PLL clock mult., the VCO i
s running
399 ; <2=> VCO clock used, input clock switched off <3=> VCO clock used, input clock conne
cted
0003 400 _PLLCTRL EQU 3 ; 0 = Bypass PLL clock mult., the VCO is off
401 ; 1 = Bypass PLL clock mult., the VCO is running
402 ; 2 = VCO clock used, input clock switched off
403 ; 3 = VCO clock used, input clock connected
404 ;
405 ; <o> PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
406 ; <0=> Register PLLCON may be written <1=> Write cycles to register PLLCON are ignore
d
0000 407 _PLLWRI EQU 0 ; 0 = Register PLLCON may be written
408 ; 1 = Write cycles to register PLLCON are ignored
409 ;</e>
410 ;
411 ; <e> Definitions for Watchdog Timer Control Register WDTCON
412 ; ==========================================================
413 ;
414 ; --- Set WATCHDOG = 0 to enable the Hardware watchdog and initilize the WDTCON regist
er
415 $SET (WATCHDOG = 0) ; 0 = Disabled Hardware watchdog
416 ;
417 ; <o> WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
418 ; <0=> Peripheral Frequency divided by 2 <1=> Peripheral Frequency divided by 128
419 ; <2=> Peripheral Frequency divided by 4 <3=> Peripheral Frequency divided by 256
0001 420 _WDTIN EQU 1 ; 0 = frequency f_peripheral / 2 (CPU default)
421 ; 1 = frequency f_peripheral / 128 (recommended for START_V2)
422 ; 2 = frequency f_peripheral / 4
423 ; 3 = frequency f_peripheral / 256
424 ;
425 ; <o> WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15) <0-255>
426 ; <i> High byte of WDT (counts up, overflow gives Watchdog reset)
0000 427 _WDTREL EQU 0
428 ;
429 ;</e>
430 ; <e> Definitions for Frequency Output Signal FOCON
431 ; =================================================
432 ;
433 ; INIT_FOCON: Init FOCON register
434 ; --- Set INIT_FOCON = 0 to initilize the FOCON register
435 $SET (INIT_FOCON = 1)
436 ;
437 ; <o> CLKEN: CLKOUT Enable (FOCON.7)
438 ; <0=> P3.15 is IO <1=> P3.15 is CLKOUT
0000 439 _CLKEN EQU 0 ; 0 = P3.15 is IO pin when _FOUT is 0
440 ; 1 = P3.15 outputs signal CLKOUT
441 ;
442 ; <o> FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13) <0-63>
443 ; <i> Is copied to FOCNT upon each underflow of FOCNT
0000 444 _FORV EQU 0
445 ;
446 ; <o> FOSS: Frequency Output Signal Select (FOCON.14)
447 ; <0=> Output of Toggle Latch <1=> Output of Reload Counter
0000 448 _FOSS EQU 0 ; 0 = Output of the toggle latch; 0.5 duty cycle
449 ; 1 = Output of reload counter; duty cycle depends on FORV
450 ;
A166 MACRO ASSEMBLER START_V2 12/10/2006 17:29:06 PAGE 8
451 ; <o> FOEN: Frequency Output Enable (FOCON.15)
452 ; <0=> P3.15 is IO <1=> P3.15 outputs f_OUT
0000 453 _FOEN EQU 0 ; 0 = P3.15 is IO pin when _CLKEN is 0
454 ; 1 = P3.15 outputs f_OUT when _CLKEN is 0
455 ;</e>
456 ;
457 ;<h> External Bus Configuration
458 ;
459 ; <e> Configure External Bus (EBC) Behaviour
460 ; ==========================================
461 ;
462 ; --- Set CONFIG_EBC = 0 to initialize the EBCMOD0/EBCMOD1 registers
463 $SET (CONFIG_EBC = 0) ; 0 = EBCMOD0/EBCMOD1 are set during reset according the
464 ; of configuration bus (typical Port0) values.
465 ; 1 = the following external bus configuration values
466 ; are written to EBCMOD and BUSACT0
467 ;
468 ; <h> Definitions for EBC Mode 0 register EBCMOD0
469 ; ===============================================
470 ;
471 ; <o> SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3) <0-8>
472 ; <i> Number of active Address Lines (A16-A23)
0000 473 _SAPEN EQU 0 ; 0 = No segment address pins enabled
474 ; 1 = One (A16) segment address pin enabled
475 ; : = :
476 ; 8 = Eight (A16 .. A23) address pins enabled
477 ; 9 - 15 = reserved
478 ;
479 ; <o> CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7) <0-8>
480 ; <i> Number of active ChipSelect pins
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