test.c

YL9200开发板的测试代码,详细请下载后细看

#include "def.h"
#include "console.h"

#define	SHOW_PIC

#ifdef SHOW_PIC
#include "test_pic.h"
#endif

#define	CONFIG_ARCH_AT91RM9200

typedef struct
{
	unsigned short index;
	unsigned short value;
} S1D_REGS;

static S1D_REGS aS1DRegs[] =
{
	{0x0001,0x00},   // Miscellaneous Register
	{0x01FC,0x00},   // Display Mode Register
	{0x0004,0x00},   // General IO Pins Configuration Register
	{0x0008,0x00},   // General IO Pins Control Register
	#ifdef CONFIG_ARCH_AT91RM9200	//hzh
	{0x0010,0x11},   // Memory Clock Configuration Register,存储器时钟内部除以2
	{0x0014,0x10},   // LCD Pixel Clock Configuration Register
	{0x0018,0x12},   // CRT/TV Pixel Clock Configuration Register
	{0x001C,0x12},   // MediaPlug Clock Configuration Register
	{0x001E,0x02},   // CPU To Memory Wait State Select Register
	{0x0020,0x00},   // Memory Configuration Register
	{0x0021,0x04},   // DRAM Refresh Rate Register, MCLK source是divid之前的值,即busclk或clki的原始输入频率
	#else
	{0x0010,0x01},   // Memory Clock Configuration Register
	{0x0014,0x00},   // LCD Pixel Clock Configuration Register
	{0x0018,0x02},   // CRT/TV Pixel Clock Configuration Register
	{0x001C,0x02},   // MediaPlug Clock Configuration Register
	{0x001E,0x01},   // CPU To Memory Wait State Select Register
	{0x0020,0x00},   // Memory Configuration Register
	{0x0021,0x04},   // DRAM Refresh Rate Register
	#endif
	{0x002A,0x12},   // DRAM Timings Control Register 0
	{0x002B,0x02},   // DRAM Timings Control Register 1
	{0x0030,0x25},   // Panel Type Register
	{0x0031,0x00},   // MOD Rate Register
	{0x0032,0x4F},   // LCD Horizontal Display Width Register
	{0x0034,0x12},   // LCD Horizontal Non-Display Period Register
	{0x0035,0x01},   // TFT FPLINE Start Position Register
	{0x0036,0x0B},   // TFT FPLINE Pulse Width Register
	{0x0038,0xDF},   // LCD Vertical Display Height Register 0
	{0x0039,0x01},   // LCD Vertical Display Height Register 1
	{0x003A,0x2C},   // LCD Vertical Non-Display Period Register
	{0x003B,0x0A},   // TFT FPFRAME Start Position Register
	{0x003C,0x01},   // TFT FPFRAME Pulse Width Register
	{0x0040,0x03},   // LCD Display Mode Register
	{0x0041,0x00},   // LCD Miscellaneous Register
	{0x0042,0x00},   // LCD Display Start Address Register 0
	{0x0043,0x00},   // LCD Display Start Address Register 1
	{0x0044,0x00},   // LCD Display Start Address Register 2
	{0x0046,0x40},   // LCD Memory Address Offset Register 0
	{0x0047,0x01},   // LCD Memory Address Offset Register 1
	{0x0048,0x00},   // LCD Pixel Panning Register
	{0x004A,0x00},   // LCD Display FIFO High Threshold Control Register
	{0x004B,0x00},   // LCD Display FIFO Low Threshold Control Register
	{0x0050,0x4F},   // CRT/TV Horizontal Display Width Register
	{0x0052,0x13},   // CRT/TV Horizontal Non-Display Period Register
	{0x0053,0x01},   // CRT/TV HRTC Start Position Register
	{0x0054,0x0B},   // CRT/TV HRTC Pulse Width Register
	{0x0056,0xDF},   // CRT/TV Vertical Display Height Register 0
	{0x0057,0x01},   // CRT/TV Vertical Display Height Register 1
	{0x0058,0x2B},   // CRT/TV Vertical Non-Display Period Register
	{0x0059,0x09},   // CRT/TV VRTC Start Position Register
	{0x005A,0x01},   // CRT/TV VRTC Pulse Width Register
	#ifdef CONFIG_ARCH_AT91RM9200	//hzh
	{0x005B,0x18},   // TV Output Control Register, 不用DAC输出增强(0x10)或增大IREF的电阻
	#else
	{0x005B,0x18},   // TV Output Control Register
	#endif
	{0x0060,0x05},   // CRT/TV Display Mode Register, 16BPP
	{0x0062,0x00},   // CRT/TV Display Start Address Register 0
	{0x0063,0x00},   // CRT/TV Display Start Address Register 1
	{0x0064,0x00},   // CRT/TV Display Start Address Register 2
	{0x0066,0x80},   // CRT/TV Memory Address Offset Register 0
	{0x0067,0x02},   // CRT/TV Memory Address Offset Register 1
	{0x0068,0x00},   // CRT/TV Pixel Panning Register
	{0x006A,0x00},   // CRT/TV Display FIFO High Threshold Control Register
	{0x006B,0x00},   // CRT/TV Display FIFO Low Threshold Control Register
	{0x0070,0x00},   // LCD Ink/Cursor Control Register
	{0x0071,0x01},   // LCD Ink/Cursor Start Address Register
	{0x0072,0x00},   // LCD Cursor X Position Register 0
	{0x0073,0x00},   // LCD Cursor X Position Register 1
	{0x0074,0x00},   // LCD Cursor Y Position Register 0
	{0x0075,0x00},   // LCD Cursor Y Position Register 1
	{0x0076,0x00},   // LCD Ink/Cursor Blue Color 0 Register
	{0x0077,0x00},   // LCD Ink/Cursor Green Color 0 Register
	{0x0078,0x00},   // LCD Ink/Cursor Red Color 0 Register
	{0x007A,0x1F},   // LCD Ink/Cursor Blue Color 1 Register
	{0x007B,0x3F},   // LCD Ink/Cursor Green Color 1 Register
	{0x007C,0x1F},   // LCD Ink/Cursor Red Color 1 Register
	{0x007E,0x00},   // LCD Ink/Cursor FIFO Threshold Register
	{0x0080,0x00},   // CRT/TV Ink/Cursor Control Register
	{0x0081,0x01},   // CRT/TV Ink/Cursor Start Address Register
	{0x0082,0x00},   // CRT/TV Cursor X Position Register 0
	{0x0083,0x00},   // CRT/TV Cursor X Position Register 1
	{0x0084,0x00},   // CRT/TV Cursor Y Position Register 0
	{0x0085,0x00},   // CRT/TV Cursor Y Position Register 1
	{0x0086,0x00},   // CRT/TV Ink/Cursor Blue Color 0 Register
	{0x0087,0x00},   // CRT/TV Ink/Cursor Green Color 0 Register
	{0x0088,0x00},   // CRT/TV Ink/Cursor Red Color 0 Register
	{0x008A,0x1F},   // CRT/TV Ink/Cursor Blue Color 1 Register
	{0x008B,0x3F},   // CRT/TV Ink/Cursor Green Color 1 Register
	{0x008C,0x1F},   // CRT/TV Ink/Cursor Red Color 1 Register
	{0x008E,0x00},   // CRT/TV Ink/Cursor FIFO Threshold Register
	{0x0100,0x00},   // BitBlt Control Register 0
	{0x0101,0x00},   // BitBlt Control Register 1
	{0x0102,0x00},   // BitBlt ROP Code/Color Expansion Register
	{0x0103,0x00},   // BitBlt Operation Register
	{0x0104,0x00},   // BitBlt Source Start Address Register 0
	{0x0105,0x00},   // BitBlt Source Start Address Register 1
	{0x0106,0x00},   // BitBlt Source Start Address Register 2
	{0x0108,0x00},   // BitBlt Destination Start Address Register 0
	{0x0109,0x00},   // BitBlt Destination Start Address Register 1
	{0x010A,0x00},   // BitBlt Destination Start Address Register 2
	{0x010C,0x00},   // BitBlt Memory Address Offset Register 0
	{0x010D,0x00},   // BitBlt Memory Address Offset Register 1
	{0x0110,0x00},   // BitBlt Width Register 0
	{0x0111,0x00},   // BitBlt Width Register 1
	{0x0112,0x00},   // BitBlt Height Register 0
	{0x0113,0x00},   // BitBlt Height Register 1
	{0x0114,0x00},   // BitBlt Background Color Register 0
	{0x0115,0x00},   // BitBlt Background Color Register 1
	{0x0118,0x00},   // BitBlt Foreground Color Register 0
	{0x0119,0x00},   // BitBlt Foreground Color Register 1
	{0x01E0,0x00},   // Look-Up Table Mode Register
	{0x01E2,0x00},   // Look-Up Table Address Register
	{0x01F0,0x00},   // Power Save Configuration Register
	{0x01F1,0x00},   // Power Save Status Register
	{0x01F4,0x00},   // CPU-to-Memory Access Watchdog Timer Register
	{0x01FC,0x02},   // Display Mode Register, CRT
	//{0x01FC,0x00},   // Display Mode Register, none

};

#define	DISP_WIDTH	640
#define	DISP_HEIGHT	480
#define	DSIP_DEPTH	16

#define	BPP16_BLACK		0x0000
#define	BPP16_WHITE		0xffff
#define	BPP16_BLUE		0x001f
#define	BPP16_GREEN		0x07e0
#define	BPP16_RED		0xf800

#define	DIS_REG_BASE	0x80000000
#define	DIS_MEM_BASE	0x80200000

static void cut_paste_test( void* mem )
{
	int x, y, i, j;
	U16 save_mem[DISP_HEIGHT][DISP_WIDTH];

	for ( y = 0; y < DISP_HEIGHT; y += 40 )
		for ( x = 0; x < DISP_WIDTH; x += 40 )
		{
			for ( j = 0; j < 40; j++ )
				for ( i = 0; i < 40; i++ )
				{
					save_mem[y + j][x + i] = ( ( U16 * ) mem )[( y + j ) * DISP_WIDTH + x + i];
					( ( U16 * ) mem )[( y + j ) * DISP_WIDTH + x + i] = BPP16_BLUE;
				}
		}

	for ( y = 0; y < DISP_HEIGHT; y += 40 )
		for ( x = 0; x < DISP_WIDTH; x += 40 )
		{
			for ( j = 0; j < 40; j++ )
				for ( i = 0; i < 40; i++ )
					( ( U16 * ) mem )[( y + j ) * DISP_WIDTH + x + i] = save_mem[y + j][x + i];
		}
}

void test_s1d13506(U32 a1,U32 a2)
{
	int i;
	U16 v;
	volatile U8* pReg = ( U8* ) DIS_REG_BASE;
	U16* pMem;


	pReg[1] = 0;
	printf( "s1d13506 version is 0x%x, " , pReg[0] );
	printf( "MD configruation is 0x%x\n" , ( pReg[0xd] << 8 ) | pReg[0xc] );
	for ( i = 0; i < sizeof( aS1DRegs ) / sizeof( aS1DRegs[0] ); i++ )
	{
		v = *( U16 * ) ( DIS_REG_BASE + ( aS1DRegs[i].index & ~1 ) );
		v &= ( aS1DRegs[i].index & 1 ) ? 0xff : ( 0xff << 8 );
		v |= ( aS1DRegs[i].index & 1 ) ? ( aS1DRegs[i].value << 8 ) : aS1DRegs[i].value;
		*( U16 * ) ( DIS_REG_BASE + ( aS1DRegs[i].index & ~1 ) ) = v;
		//pReg[aS1DRegs[i].index] = aS1DRegs[i].value;
	}
	/*	
		while(1) {
			*(volatile U16 *)0x80200000 = 0x55aa;
			v = *(volatile U16 *)0x80200000;
			//pReg[1] = 0;
			//v = pReg[0];
	//		printf("%x\n", v);
		}
	*/
	/*	while(1) {
			pReg[0x57] = 1;
			pReg[0x56] = 0xdf;
	//		i = pReg[0];
		}
	*/
	printf( "h : 0x%x\n" , pReg[0x50] );
	printf( "v : 0x%x\n" , ( pReg[0x57] << 8 ) | pReg[0x56] );

	pMem = ( U16 * ) DIS_MEM_BASE;
	i = 0;
	for ( ; i < 640 * 160; i++ )
		pMem[i] = BPP16_RED;
	for ( ; i < 640 * 320; i++ )
		pMem[i] = BPP16_GREEN;
	for ( ; i < 640 * 480; i++ )
		pMem[i] = BPP16_BLUE;
	puts("Please any key to continue\n");
	getch();
#if 1	
	//while(1) {
		for(i=0; i<640*480; i++)
			pMem[i] = BPP16_RED;
		for(i=0; i<640*480; i++)
			pMem[i] = BPP16_GREEN;
		for(i=0; i<640*480; i++)
			pMem[i] = BPP16_BLUE;
		for(i=0; i<640*480; i++)
			pMem[i] = BPP16_WHITE;
		for(i=0; i<640*480; i++)
			pMem[i] = BPP16_BLACK;
	//}
#endif
	puts("Please any key to continue\n");
	getch();
#ifdef SHOW_PIC
	for ( i = 0; i < 640 * 480; i++ )
		pMem[i] = ( girl0_640_480[2 * i] << 8 ) | girl0_640_480[2 * i + 1];
#endif

	//	while(1)
	//		cut_paste_test(pMem);
}