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📄 sed1356.c

📁 YL9200开发板的测试代码,详细请下载后细看
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	{0x0078,0x00},   // LCD Ink/Cursor Red Color 0 Register
	{0x007A,0x1F},   // LCD Ink/Cursor Blue Color 1 Register
	{0x007B,0x3F},   // LCD Ink/Cursor Green Color 1 Register
	{0x007C,0x1F},   // LCD Ink/Cursor Red Color 1 Register
	{0x007E,0x00},   // LCD Ink/Cursor FIFO Threshold Register
	{0x0080,0x00},   // CRT/TV Ink/Cursor Control Register
	{0x0081,0x01},   // CRT/TV Ink/Cursor Start Address Register
	{0x0082,0x00},   // CRT/TV Cursor X Position Register 0
	{0x0083,0x00},   // CRT/TV Cursor X Position Register 1
	{0x0084,0x00},   // CRT/TV Cursor Y Position Register 0
	{0x0085,0x00},   // CRT/TV Cursor Y Position Register 1
	{0x0086,0x00},   // CRT/TV Ink/Cursor Blue Color 0 Register
	{0x0087,0x00},   // CRT/TV Ink/Cursor Green Color 0 Register
	{0x0088,0x00},   // CRT/TV Ink/Cursor Red Color 0 Register
	{0x008A,0x1F},   // CRT/TV Ink/Cursor Blue Color 1 Register
	{0x008B,0x3F},   // CRT/TV Ink/Cursor Green Color 1 Register
	{0x008C,0x1F},   // CRT/TV Ink/Cursor Red Color 1 Register
	{0x008E,0x00},   // CRT/TV Ink/Cursor FIFO Threshold Register
	{0x0100,0x00},   // BitBlt Control Register 0
	{0x0101,0x01},   // BitBlt Control Register 1
	{0x0102,0x00},   // BitBlt ROP Code/Color Expansion Register
	{0x0103,0x00},   // BitBlt Operation Register
	{0x0104,0x00},   // BitBlt Source Start Address Register 0
	{0x0105,0x00},   // BitBlt Source Start Address Register 1
	{0x0106,0x00},   // BitBlt Source Start Address Register 2
	{0x0108,0x00},   // BitBlt Destination Start Address Register 0
	{0x0109,0x00},   // BitBlt Destination Start Address Register 1
	{0x010A,0x00},   // BitBlt Destination Start Address Register 2
	{0x010C,0x00},   // BitBlt Memory Address Offset Register 0
	{0x010D,0x00},   // BitBlt Memory Address Offset Register 1
	{0x0110,0x00},   // BitBlt Width Register 0
	{0x0111,0x00},   // BitBlt Width Register 1
	{0x0112,0x00},   // BitBlt Height Register 0
	{0x0113,0x00},   // BitBlt Height Register 1
	{0x0114,0x00},   // BitBlt Background Color Register 0
	{0x0115,0x00},   // BitBlt Background Color Register 1
	{0x0118,0x00},   // BitBlt Foreground Color Register 0
	{0x0119,0x00},   // BitBlt Foreground Color Register 1
	{0x01E0,0x00},   // Look-Up Table Mode Register
	{0x01E2,0x00},   // Look-Up Table Address Register
	{0x01F0,0x00},   // Power Save Configuration Register
	{0x01F1,0x00},   // Power Save Status Register
	{0x01F4,0x00},   // CPU-to-Memory Access Watchdog Timer Register
	{0x01FC,0x01},   // Display Mode Register, LCD only
};

//*****************************************************************************
static SED_REGS SED_Reg_LCD640480[] =		//LCD640480模式下寄存器参数配置表格
{
	{0x0001,0x00},   // Miscellaneous Register
	{0x01FC,0x01},   // Display Mode Register, LCD only
	{0x0004,0x00},   // General IO Pins Configuration Register
	{0x0008,0x00},   // General IO Pins Control Register
	
#ifdef CONFIG_ARCH_AT91RM9200	//hzh
	{0x0010,0x11},   // Memory Clock Configuration Register,存储器时钟内部除以2
	{0x0014,0x10},   // LCD Pixel Clock Configuration Register
	{0x0018,0x12},   // CRT/TV Pixel Clock Configuration Register
	{0x001C,0x01},   // MediaPlug Clock Configuration Register
	{0x001E,0x02},   // CPU To Memory Wait State Select Register
	{0x0020,0x00},   // Memory Configuration Register
	{0x0021,0x04},   // DRAM Refresh Rate Register, MCLK source是divid之前的值,即busclk或clki的原始输入频率
#else
	{0x0010,0x01},   // Memory Clock Configuration Register
	{0x0014,0x00},   // LCD Pixel Clock Configuration Register
	{0x0018,0x02},   // CRT/TV Pixel Clock Configuration Register
	{0x001C,0x02},   // MediaPlug Clock Configuration Register
	{0x001E,0x01},   // CPU To Memory Wait State Select Register
	{0x0020,0x00},   // Memory Configuration Register
	{0x0021,0x04},   // DRAM Refresh Rate Register
#endif

//	#define VBPD_640480		(24)	//垂直同步信号的后肩
//	#define VFPD_640480		(10)		//垂直同步信号的前肩*
//	#define VSPW_640480		(2)		//垂直同步信号的脉宽
//	
//	#define HBPD_640480		(44)		//水平同步信号的后肩
//	#define HFPD_640480		(16)		//水平同步信号的前肩*
//	#define HSPW_640480		(96)		//水平同步信号的脉宽

	{0x002A,0x12},   // DRAM Timings Control Register 0
	{0x002B,0x02},   // DRAM Timings Control Register 1
	{0x0030,0x25},   // Panel Type Register
	{0x0031,0x00},   // MOD Rate Register
	{0x0032,(LCD640480_XSIZE/8-1)},   // LCD Horizontal Display Width Register
	{0x0034,0x13},   // LCD Horizontal Non-Display Period Register
	{0x0035,0x01},   // TFT FPLINE Start Position Register
	{0x0036,0x0c},   // TFT FPLINE Pulse Width Register
	{0x0038,((LCD640480_YSIZE-1)%256)},   // LCD Vertical Display Height Register 0
	{0x0039,((LCD640480_YSIZE-1)/256)},   // LCD Vertical Display Height Register 1
	{0x003A,0x2c},   // LCD Vertical Non-Display Period Register
	{0x003B,0x0a},   // TFT FPFRAME Start Position Register
	{0x003C,0x02},   // TFT FPFRAME Pulse Width Register
	{0x0040,0x05},   // LCD Display Mode Register
	{0x0041,0x01},   // LCD Miscellaneous Register
	{0x0042,0x00},   // LCD Display Start Address Register 0
	{0x0043,0x00},   // LCD Display Start Address Register 1
	{0x0044,0x00},   // LCD Display Start Address Register 2
	{0x0046,((LCD640480_XSIZE)%256)},   // LCD Memory Address Offset Register 0
	{0x0047,((LCD640480_XSIZE)/256)},   // LCD Memory Address Offset Register 1
	{0x0048,0x03},   // LCD Pixel Panning Register
	{0x004A,0x00},   // LCD Display FIFO High Threshold Control Register
	{0x004B,0x00},   // LCD Display FIFO Low Threshold Control Register
	{0x0050,0x4F},   // CRT/TV Horizontal Display Width Register
	{0x0052,0x13},   // CRT/TV Horizontal Non-Display Period Register
	{0x0053,0x01},   // CRT/TV HRTC Start Position Register
	{0x0054,0x0B},   // CRT/TV HRTC Pulse Width Register
	{0x0056,0xDF},   // CRT/TV Vertical Display Height Register 0
	{0x0057,0x01},   // CRT/TV Vertical Display Height Register 1
	{0x0058,0x2B},   // CRT/TV Vertical Non-Display Period Register
	{0x0059,0x09},   // CRT/TV VRTC Start Position Register
	{0x005A,0x01},   // CRT/TV VRTC Pulse Width Register

#ifdef CONFIG_ARCH_AT91RM9200	//hzh
	{0x005B,0x18},   // TV Output Control Register, 不用DAC输出增强(0x10)或增大IREF的?
	{0x005B,0x18},   // TV Output Control Register
#endif

	{0x0060,0x05},   // CRT/TV Display Mode Register, 16BPP
	{0x0062,0x00},   // CRT/TV Display Start Address Register 0
	{0x0063,0x00},   // CRT/TV Display Start Address Register 1
	{0x0064,0x00},   // CRT/TV Display Start Address Register 2
	{0x0066,0x80},   // CRT/TV Memory Address Offset Register 0
	{0x0067,0x02},   // CRT/TV Memory Address Offset Register 1
	{0x0068,0x00},   // CRT/TV Pixel Panning Register
	{0x006A,0x00},   // CRT/TV Display FIFO High Threshold Control Register
	{0x006B,0x00},   // CRT/TV Display FIFO Low Threshold Control Register
	{0x0070,0x00},   // LCD Ink/Cursor Control Register
	{0x0071,0x01},   // LCD Ink/Cursor Start Address Register
	{0x0072,0x00},   // LCD Cursor X Position Register 0
	{0x0073,0x00},   // LCD Cursor X Position Register 1
	{0x0074,0x00},   // LCD Cursor Y Position Register 0
	{0x0075,0x00},   // LCD Cursor Y Position Register 1
	{0x0076,0x00},   // LCD Ink/Cursor Blue Color 0 Register
	{0x0077,0x00},   // LCD Ink/Cursor Green Color 0 Register
	{0x0078,0x00},   // LCD Ink/Cursor Red Color 0 Register
	{0x007A,0x1F},   // LCD Ink/Cursor Blue Color 1 Register
	{0x007B,0x3F},   // LCD Ink/Cursor Green Color 1 Register
	{0x007C,0x1F},   // LCD Ink/Cursor Red Color 1 Register
	{0x007E,0x00},   // LCD Ink/Cursor FIFO Threshold Register
	{0x0080,0x00},   // CRT/TV Ink/Cursor Control Register
	{0x0081,0x01},   // CRT/TV Ink/Cursor Start Address Register
	{0x0082,0x00},   // CRT/TV Cursor X Position Register 0
	{0x0083,0x00},   // CRT/TV Cursor X Position Register 1
	{0x0084,0x00},   // CRT/TV Cursor Y Position Register 0
	{0x0085,0x00},   // CRT/TV Cursor Y Position Register 1
	{0x0086,0x00},   // CRT/TV Ink/Cursor Blue Color 0 Register
	{0x0087,0x00},   // CRT/TV Ink/Cursor Green Color 0 Register
	{0x0088,0x00},   // CRT/TV Ink/Cursor Red Color 0 Register
	{0x008A,0x1F},   // CRT/TV Ink/Cursor Blue Color 1 Register
	{0x008B,0x3F},   // CRT/TV Ink/Cursor Green Color 1 Register
	{0x008C,0x1F},   // CRT/TV Ink/Cursor Red Color 1 Register
	{0x008E,0x00},   // CRT/TV Ink/Cursor FIFO Threshold Register
	{0x0100,0x00},   // BitBlt Control Register 0
	{0x0101,0x01},   // BitBlt Control Register 1
	{0x0102,0x00},   // BitBlt ROP Code/Color Expansion Register
	{0x0103,0x00},   // BitBlt Operation Register
	{0x0104,0x00},   // BitBlt Source Start Address Register 0
	{0x0105,0x00},   // BitBlt Source Start Address Register 1
	{0x0106,0x00},   // BitBlt Source Start Address Register 2
	{0x0108,0x00},   // BitBlt Destination Start Address Register 0
	{0x0109,0x00},   // BitBlt Destination Start Address Register 1
	{0x010A,0x00},   // BitBlt Destination Start Address Register 2
	{0x010C,0x00},   // BitBlt Memory Address Offset Register 0
	{0x010D,0x00},   // BitBlt Memory Address Offset Register 1
	{0x0110,0x00},   // BitBlt Width Register 0
	{0x0111,0x00},   // BitBlt Width Register 1
	{0x0112,0x00},   // BitBlt Height Register 0
	{0x0113,0x00},   // BitBlt Height Register 1
	{0x0114,0x00},   // BitBlt Background Color Register 0
	{0x0115,0x00},   // BitBlt Background Color Register 1
	{0x0118,0x00},   // BitBlt Foreground Color Register 0
	{0x0119,0x00},   // BitBlt Foreground Color Register 1
	{0x01E0,0x00},   // Look-Up Table Mode Register
	{0x01E2,0x00},   // Look-Up Table Address Register
	{0x01F0,0x00},   // Power Save Configuration Register
	{0x01F1,0x00},   // Power Save Status Register
	{0x01F4,0x00},   // CPU-to-Memory Access Watchdog Timer Register
	{0x01FC,0x01},   // Display Mode Register, LCD only
};

/********************************************************************************************************************
【函数名称】void Test_Vedio_Memory_Cut_Paste( void* mem )
【功能描述】显示存储器读写测试,主要用来测试显示速度
【参数输入】显示存储器的地址指针
【参数返回】无
********************************************************************************************************************/
void Test_Vedio_Memory_Cut_Paste( void* mem )
{
	int x, y, i, j;
	U16 save_mem[VGA_YSIZE][VGA_XSIZE];

	for ( y = 0; y < VGA_YSIZE; y += 40 )
		for ( x = 0; x < VGA_XSIZE; x += 40 )
		{
			for ( j = 0; j < 40; j++ )
				for ( i = 0; i < 40; i++ )
				{
					save_mem[y + j][x + i] = ( ( U16 * ) mem )[( y + j ) * VGA_XSIZE + x + i];
					( ( U16 * ) mem )[( y + j ) * VGA_XSIZE + x + i] = BPP16_BLUE;
				}
		}

	for ( y = 0; y < VGA_YSIZE; y += 40 )
		for ( x = 0; x < VGA_XSIZE; x += 40 )
		{
			for ( j = 0; j < 40; j++ )
				for ( i = 0; i < 40; i++ )
					( ( U16 * ) mem )[( y + j ) * VGA_XSIZE + x + i] = save_mem[y + j][x + i];
		}
}

/*******************************************************************************************************************
【函数名称】void PutPixel_16BPP240320( U32 x, U32 y, U16 c )
【功能描述】16BPP模式240×320分辨率下单个象素的显示数据设置
【参数输入】x为X坐标,y为Y坐标,c为象素的值
【参数返回】无
********************************************************************************************************************/
void PutPixel_16BPP240320( U32 x, U32 y, U16 c )
{
	U16* pMem = ( U16 * ) DIS_MEM_BASE ;
	
	pMem[ (y*240) + x ] = c  ;
	/*pMem[ (y*240) + x ] =
		( ( ( c & 0x8000 ) >> 15 ) <<  0 ) |
		( ( ( c & 0x4000 ) >> 14 ) <<  1 ) | 
		( ( ( c & 0x2000 ) >> 13 ) <<  5 ) | 
		( ( ( c & 0x1000 ) >> 12 ) <<  6 ) | 
		( ( ( c & 0x0800 ) >> 11 ) <<  7 ) | 
		( ( ( c & 0x0400 ) >> 10 ) << 11 ) | 
		( ( ( c & 0x0200 ) >>  9 ) << 12 ) | 
		( ( ( c & 0x0100 ) >>  8 ) <<  2 ) | 
		( ( ( c & 0x0080 ) >>  7 ) <<  3 ) | 
		( ( ( c & 0x0040 ) >>  6 ) <<  4 ) | 
		( ( ( c & 0x0020 ) >>  5 ) <<  8 ) | 
		( ( ( c & 0x0010 ) >>  4 ) <<  9 ) | 
		( ( ( c & 0x0008 ) >>  3 ) << 10 ) | 
		( ( ( c & 0x0004 ) >>  2 ) << 13 ) | 
		( ( ( c & 0x0002 ) >>  1 ) << 14 ) | 
		( ( ( c & 0x0001 ) >>  0 ) << 15 ) ; */
}

/*******************************************************************************************************************
【函数名称】void PutPixel_16BPP640480( U32 x, U32 y, U16 c )
【功能描述】16BPP模式640×480分辨率下单个象素的显示数据设置
【参数输入】x为X坐标,y为Y坐标,c为象素的值
【参数返回】无
********************************************************************************************************************/
void PutPixel_16BPP640480( U32 x, U32 y, U16 c )
{
	U16* pMem = ( U16 * ) DIS_MEM_BASE ;
	
	pMem[ (y*640) + x ] = c ;
	/*pMem[ (y*640) + x ] =
		( ( ( c & 0x8000 ) >> 15 ) <<  0 ) |
		( ( ( c & 0x4000 ) >> 14 ) <<  1 ) | 
		( ( ( c & 0x2000 ) >> 13 ) <<  5 ) | 
		( ( ( c & 0x1000 ) >> 12 ) <<  6 ) | 
		( ( ( c & 0x0800 ) >> 11 ) <<  7 ) | 
		( ( ( c & 0x0400 ) >> 10 ) << 11 ) | 
		( ( ( c & 0x0200 ) >>  9 ) << 12 ) | 
		( ( ( c & 0x0100 ) >>  8 ) <<  2 ) | 
		( ( ( c & 0x0080 ) >>  7 ) <<  3 ) | 
		( ( ( c & 0x0040 ) >>  6 ) <<  4 ) | 
		( ( ( c & 0x0020 ) >>  5 ) <<  8 ) | 
		( ( ( c & 0x0010 ) >>  4 ) <<  9 ) | 
		( ( ( c & 0x0008 ) >>  3 ) << 10 ) | 
		( ( ( c & 0x0004 ) >>  2 ) << 13 ) | 
		( ( ( c & 0x0002 ) >>  1 ) << 14 ) |
		( ( ( c & 0x0001 ) >>  0 ) << 15 ) ; */

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