uss_dpopns.s

VXWORKS源代码

        jne     DNANRS          | J/ INF - INF -> NaN
        jra     DINFRS          |    INF + INF -> INF
|
|
DPA010:
        cmpiw   #0x7FF,d1
        jne     DPA040          | J/ not NaN or INF
|
        lsll    #1,d4           | Remove implicit bit
        jne     DNANRS          | J/ NaN + 0,num -> NaN
|
        moveal  a3,a2           | Move sign over
        jra     DINFRS          | INF result
|
|
DPXSUB:
        |dsw    0               | Entry for DPCMP
|
DPA040:
        andw    d1,d1
        jeq     DOPRSL          | J/ 0,num + 0 -> 0,num
|
        andw    d0,d0
        jne     DPA045          | J/ no zeroes involved
|
        movew   d1,d0           | Copy over data
        movel   d4,d2
        movel   d5,d3
        moveal  a3,a2
        jra     DOPRSL
|
|
DPA045:
        |dsw    0
|
        cmpw    d1,d0
        jcc     DPA060          | J/ op1.exp >= op2.exp
|
        exg     d2,d4           | Flip mantissas
        exg     d3,d5
        exg     d0,d1
        exg     a2,a3
|
DPA060:
        subw    d0,d1
        negw    d1
        cmpiw   #53,d1
        jhi     DOPRSL          | J/ op2 too small to matter
|
        cmpiw   #32,d1
        jlt     DPA061          | J/ less than a word shift
|
        movel   d4,d5
        clrl    d4
|
        subiw   #32,d1
|
DPA061:
        cmpiw   #16,d1
        jlt     DPA062          | J/ less than a swap shift left
|
        movew   d4,d5           | Do a swap shift (16 bits)
        clrw    d4
        swap    d5
        swap    d4
|
        subiw   #16,d1
|
DPA062:
        moveq   #-1,d7          | Mask in d7
        lsrl    d1,d7
        rorl    d1,d4
        rorl    d1,d5
        andl    d7,d5           | Trim bits
        eorl    d4,d5           | Mix in d4 -> d5 bits
        andl    d7,d4           | Strip d4 -> d5 bits
        eorl    d4,d5           | Finish   LSL  d0,d4:d5
|
        cmpal   a2,a3
        jne     DPS100          | J/ subtract operation
|
        addl    d5,d3
        addxl   d4,d2
        jcc     DOPRSL          | J/ no carry out
|
        roxrl   #1,d2           | Handle carry out
        roxrl   #1,d3
        addqw   #1,d0           | Bump the exponent
        jra     DOPRSL
|
|
DPS100:
        subl    d5,d3           | Do the subtract
        subxl   d4,d2
        jcc     DPS110
|
        negl    d3
        negxl   d2
|
        moveal  a3,a2           | Flip sign
|
DPS110:
        andl    d2,d2           | Normalization section
        jne     DPS115          | J/ top word is not zero
|
        exg     d2,d3
        subiw   #32,d0          | Reduce exponent appropriately
|
        andl    d2,d2
        jeq     DZERRS          | J/ zero result
|
DPS115:
        cmpil   #0x0000FFFF,d2
        jhi     DPS118          | J/ less than a swap shift left
|
        swap    d2              | Do a swap shift (16 bits)
        swap    d3
        movew   d3,d2
        clrw    d3
|
        subiw   #16,d0
|
DPS118:
        tstl    d2
        jmi     DOPRSL          | J/ normalized
|
        subqw   #1,d0           | Decrease exponent value
DPS120:
        lsll    #1,d3
        roxll   #1,d2
        dbmi    d0,DPS120       | J/ not normalized
|
        jra     DOPRSL
/*
|
|       page
|
|  DPMUL
|  =====
|  Single precision multiply routine.
|
*/

DPMUL:
        bsr     GETDP2          | Fetch both operands
        movew   a2,d6
        movew   a3,d7
        eorw    d6,d7
        moveaw  d7,a2           | /* Result's sign */
|
        andw    d0,d0
        jne     DPM010          | J/ operand <> 0.0
|
        cmpiw   #0x7FF,d1
        jeq     DNANRS          | J/ 0.0 * NaN,INF -> NaN
        jra     DZERRS          | J/ 0.0 * 0.0,num -> 0.0
|
DPM010:
        cmpiw   #0x7FF,d0
        jne     DPM020          | J/ operand is a number
|
        lsll    #1,d2
        jne     DNANRS          | J/ NaN *  ?  -> NaN
|
        andw    d1,d1
        jeq     DNANRS          | J/ INF * 0.0 -> NaN
|
        cmpiw   #0x7FF,d1
        jne     DINFRS          | J/ INF * num -> INF
        lsll    #1,d4
        jeq     DINFRS          | J/ INF * INF -> INF
        jra     DNANRS          | J/ INF * NaN -> NaN
|
DPM020:
        andw    d1,d1
        jeq     DZERRS          | J/ num * 0.0 -> 0.0
|
        cmpiw   #0x7FF,d1
        jne     DPM040          | J/ num * num
|
        lsll    #1,d4
        jeq     DINFRS          | J/ num * INF -> INF
        jra     DNANRS          | J/ num * NaN -> NaN
|
|
DPM040:
        addw    d1,d0           | Calculate result`s exponent
        subw    #DBIAS-1,d0     | Remove double bias, assume shift
        movew   d0,a3           | Save exponent in a3, free up d0
|
DPM050:
        |dsw    0               | Entry for DPDIV......
        movel   d2,d0           | A * D
        movel   d5,d1
#if (CPU != MC68000 && CPU != MC68010)
|       ifne    comp64-1        ;+++++
        mulul   d0,d0:d1
#else
        bsr     DPM500          | 32 x 32 partial multiply
#endif
|       endc                    ;+++++
        movel   d0,d5           | Save word
|
        movel   d3,d0           | B * C
        movel   d4,d1
#if (CPU != MC68000 && CPU != MC68010)
|       ifne    comp64-1        ;+++++
        mulul   d0,d0:d1
#else
        bsr     DPM500          | 32 x 32 partial multiply
#endif
|       endc                    ;+++++
        movel   d0,d3
|
        movel   d2,d0           | A * C
        movel   d4,d1

#if (CPU != MC68000 && CPU != MC68010)
|       ifne    comp64-1        ;+++++
        mulul   d0,d0:d1
#else
        bsr     DPM500          | 32 x 32 partial multiply
#endif
|       endc                    ;+++++
|
        clrl    d2              | Sum partial multiply results
        addl    d5,d3
        addxl   d2,d2           | Preserve possible carry out
        addl    d1,d3
        addxl   d0,d2
        movew   a3,d0           | Restore exponent
|
        tstl    d2              | Check for normalized result
        jmi     DOPRSL          | J/ result normalized
|
        asll    #1,d3           | One left shift to normalize
        roxll   #1,d2
        subqw   #1,d0
        jra     DOPRSL

#if (CPU == MC68000 || CPU == MC68010)
|       ifne    comp64-1        ;+++++
|
|  DPM500: 32 x 32 partial multiply routine
|
|  Multiply D0 by D1 (long words) yielding a 64 bit result.
|
DPM500:
        movew   d0,d6           | Copy over B
        swap    d1
        mulu    d1,d6           | Produce BC
        swap    d0
        swap    d1
        movew   d1,d7
        mulu    d0,d7           | Produce AD
        addl    d6,d7           | Produce BC+AD in d6:d7
        subxl   d6,d6
        negl    d6
        swap    d6              | Properly position BC+AD
        swap    d7
        movew   d7,d6
|
        movew   d1,d7           | Save D (slide in under BC+AD)
        swap    d1
        mulu    d0,d1           | Produce AC
        swap    d0
        mulu    d7,d0
        clrw    d7              | Restore d6:d7
        exg     d0,d1           | AC:BD, then result, in d0:d1
        addl    d7,d1
        addxl   d6,d0
        rts
#endif
/*
|       endc                    ;+++++
|
|       page
|
|  DPDIV
|  =====
|  Double precision division operation.
|
*/

DPRDIV:
        bsr     GETDP2          | Get both operands
        exg     a2,a3           | Flip the operands
        exg     d0,d1
        exg     d2,d4
        exg     d3,d5
        jra     DPD001
|
DPDIV:
        bsr     GETDP2
|
DPD001:
        movew   a2,d6           | /* Compute result's sign */
        movew   a3,d7
        eorw    d6,d7
        moveaw  d7,a2
|
        andw    d0,d0
        jne     DPD010          | J/ divisor is not zero
|
        andw    d1,d1
        jeq     DNANRS          | J/ 0.0 / 0.0 -> NaN
        cmpiw   #0x7FF,d1
        jne     DINFRS          | J/ num / 0.0 -> INF
        lsll    #1,d4
        jeq     DINFRS          | J/ INF / 0.0 -> INF
        jra     DNANRS          | J/ NaN / 0.0 -> NaN
|
DPD010:
        cmpiw   #0x7FF,d0
        jne     DPD020          | J/ divisor is a normal number
|
        lsll    #1,d2
        jne     DNANRS          | J/  ?  / NaN -> NaN
        andw    d1,d1
        jeq     DZERRS          | J/ 0.0 / INF -> 0.0
        cmpiw   #0x7FF,d1
        jne     DUNFRS          | J/ num / INF -> 0.0 (w/ underflow)
        jra     DNANRS          | J/ NaN,INF / INF -> NaN
|
DPD020:
        andw    d1,d1
        jeq     DZERRS          | J/ 0.0 / num -> 0.0
        cmpiw   #0x7FF,d1
        jne     DPD040          | J/ num / num
|
        lsll    #1,d4
        jeq     DINFRS          | J/ INF / num -> INF
        jra     DNANRS          | J/ NaN / num -> NaN

DPD040:
#if (CPU != MC68000 && CPU != MC68010)
        subw    d0,d1
        addw    #DBIAS,d1
        movew   d1,d0
        lsrl    #1,d4
        roxrl   #1,d5
        divul   d2,d4:d5
        movel   d5,d7
        mulul   d3,d6:d7
        negl    d7
        subxl   d6,d4
        jcc     dpd54
dpd53:
        subl    #1,d5
        addl    d3,d7
        addxl   d2,d4
        jcc     dpd53
        cmpl    d2,d4
        jne     dpd54
        addl    #1,d5
        clrl    d3
        jra     dpd55
dpd54:
        divul   d2,d4:d7
        movel   d7,d3
dpd55:
        movel   d5,d2
        jmi     dpd52
        addl    d3,d3
        addxl   d2,d2
        subl    #1,d0
dpd52:
        jra     DOPRSL


#else

|       ifne    comp64-1        ;+++++
|
/*
|  Division Algorithm:
|
|  (1)  Use a two stage recipication approximation to obtain 1/B
|       (a)  X0 = 1 / (B0 + B1)    (B0 is ms 16 bits of B, B1 = B - B0)
|               = 1/B0 * (1 - B1/B0)  { accurate to 28+ bits)
|       (b)  X1 = X0 * (2 - B*X0)  (N-R iteration, 55+ bits accuracy)
|  (2)  Use DPMUL entry to produce A * X1 (64 bit computation)
*/

|
|
|DPD040:
        subw    d0,d1
        addw    #DBIAS,d1               | Restore bias
        movew   d1,a3           | Save exponent in a3
|
        movel   d5,sp@- | Save dividend mantissa on stack
        movel   d4,sp@-
|
        moveq   #1,d6           | Create a 1.0 entry
        rorl    #2,d6           | Set d4 = 4000 0000H
        swap    d2
        divu    d2,d6           | Top fifteen bits of 1/B
        movew   d6,d4           | 1/B ultimately into d4:d5
        movew   d6,d7           | Save for correction term
        swap    d4              | Position MS word
        clrw    d6              | Zero low order bits in d6