pentiumalib.s

VXWORKS源代码

/* pentiumALib.s - Pentium and PentiumPro specific routines */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01e,21aug01,hdn  added P5/P6 PMC routines
01d,24mar99,jdi  doc: added basic formatting commands, absent despite
		 thorough and long-standing coverage in WRS Coding Conventions.
01b,17apr98,hdn  fixed typo.
01b,17apr98,hdn  added documentation.
01a,09jul97,hdn  written.
*/

/*
DESCRIPTION
This module contains Pentium and PentiumPro specific routines written in 
assembly language.

.SS "MCA (Machine Check Architecture)"
The Pentium processor introduced a new exception called the machine-check 
exception (interrupt-18).  This exception is used to signal hardware-related
errors, such as a parity error on a read cycle.  The PentiumPro processor
extends the types of errors that can be detected and that generate a machine-
check exception.  It also provides a new machine-check architecture that
records information about a machine-check error and provides the basis for an
extended error logging capability.

MCA is enabled and its status registers are cleared zero in sysHwInit().
Its registers are accessed by pentiumMsrSet() and pentiumMsrGet().

.SS "PMC (Performance Monitoring Counters)"
The P5 and P6 family of processor has two performance-monitoring counters for
use in monitoring internal hardware operations.  These counters are duration
or event counters that can be programmed to count any of approximately 100
different types of events, such as the number of instructions decoded, number
of interrupts received, or number of cache loads. However, the set of events
can be counted with PMC is different in the P5 and P6 family of processors;
and the locations and bit difinitions of the related counter and control
registers are also different. So there are two set of PMC routines, one for
P6 family and one for p5 family respectively.

There are nine routines to interface the PMC of P6 family processors.  These
nine routines are:
.CS
  STATUS pentiumP6PmcStart
         (
	 int pmcEvtSel0;	/@ performance event select register 0 @/
	 int pmcEvtSel1;	/@ performance event select register 1 @/
         )
  void   pentiumP6PmcStop (void)
  void   pentiumP6PmcStop1 (void)
  void   pentiumP6PmcGet
	 (
	 long long int * pPmc0;	/@ performance monitoring counter 0 @/
	 long long int * pPmc1;	/@ performance monitoring counter 1 @/
	 )
  void   pentiumP6PmcGet0
	 (
	 long long int * pPmc0;	/@ performance monitoring counter 0 @/
	 )
  void   pentiumP6PmcGet1
	 (
	 long long int * pPmc1;	/@ performance monitoring counter 1 @/
	 )
  void   pentiumP6PmcReset (void)
  void   pentiumP6PmcReset0 (void)
  void   pentiumP6PmcReset1 (void)
.CE
pentiumP6PmcStart() starts both PMC0 and PMC1. 
pentiumP6PmcStop() stops them, and pentiumP6PmcStop1() stops only PMC1.  
pentiumP6PmcGet() gets contents of PMC0 and PMC1.  pentiumP6PmcGet0() gets
contents of PMC0, and pentiumP6PmcGet1() gets contents of PMC1.
pentiumP6PmcReset() resets both PMC0 and PMC1.  pentiumP6PmcReset0() resets
PMC0, and pentiumP6PmcReset1() resets PMC1.
PMC is enabled in sysHwInit().  Selected events in the default configuration
are PMC0 = number of hardware interrupts received and PMC1 = number of 
misaligned data memory references.

There are ten routines to interface the PMC of P5 family processors.  These
ten routines are:
.CS
  STATUS pentiumP5PmcStart0
         (
	 int pmc0Cesr;	/@ PMC0 control and event select @/
         )
  STATUS pentiumP5PmcStart1
         (
	 int pmc1Cesr;	/@ PMC1 control and event select @/
         )
  void   pentiumP5PmcStop0 (void)
  void   pentiumP5PmcStop1 (void)
  void   pentiumP5PmcGet
	 (
	 long long int * pPmc0;	/@ performance monitoring counter 0 @/
	 long long int * pPmc1;	/@ performance monitoring counter 1 @/
	 )
  void   pentiumP5PmcGet0
	 (
	 long long int * pPmc0;	/@ performance monitoring counter 0 @/
	 )
  void   pentiumP5PmcGet1
	 (
	 long long int * pPmc1;	/@ performance monitoring counter 1 @/
	 )
  void   pentiumP5PmcReset (void)
  void   pentiumP5PmcReset0 (void)
  void   pentiumP5PmcReset1 (void)
.CE
pentiumP5PmcStart0() starts PMC0, and pentiumP5PmcStart1() starts PMC1. 
pentiumP5PmcStop0() stops PMC0, and pentiumP5PmcStop1() stops PMC1.  
pentiumP5PmcGet() gets contents of PMC0 and PMC1.  pentiumP5PmcGet0() gets
contents of PMC0, and pentiumP5PmcGet1() gets contents of PMC1.
pentiumP5PmcReset() resets both PMC0 and PMC1.  pentiumP5PmcReset0() resets
PMC0, and pentiumP5PmcReset1() resets PMC1.
PMC is enabled in sysHwInit().  Selected events in the default configuration
are PMC0 = number of hardware interrupts received and PMC1 = number of 
misaligned data memory references.

.SS "MSR (Model Specific Register)"
The concept of model-specific registers (MSRs) to control hardware functions
in the processor or to monitor processor activity was introduced in the 
PentiumPro processor.  The new registers control the debug extensions, the 
performance counters, the machine-check exception capability, the machine
check architecture, and the MTRRs.  The MSRs can be read and written to using
the RDMSR and WRMSR instructions, respectively.

There are two routines to interface the MSR.  These two routines are:
.CS
  void pentiumMsrGet
       (
       int address,		/@ MSR address @/
       long long int * pData	/@ MSR data @/
       )

  void pentiumMsrSet
       (
       int address,		/@ MSR address @/
       long long int * pData	/@ MSR data @/
       )
.CE
pentiumMsrGet() get contents of the specified MSR, and 
pentiumMsrSet() sets value to the specified MSR.

.SS "TSC (Time Stamp Counter)"
The PentiumPro processor provides a 64-bit time-stamp counter that is 
incremented every processor clock cycle.  The counter is incremented even
when the processor is halted by the HLT instruction or the external STPCLK#
pin.  The time-stamp counter is set to 0 following a hardware reset of the
processor.  The RDTSC instruction reads the time stamp counter and is 
guaranteed to return a monotonically increasing unique value whenever 
executed, except for 64-bit counter wraparound.  Intel guarantees, 
architecturally, that the time-stamp counter frequency and configuration will
be such that it will not wraparound within 10 years after being reset to 0.
The period for counter wrap is several thousands of years in the PentiumPro
and Pentium processors.

There are three routines to interface the TSC.  These three routines are:
.CS
  void pentiumTscReset (void)

  void pentiumTscGet32 (void)

  void pentiumTscGet64
       (
       long long int * pTsc	/@ TSC @/
       )
.CE
pentiumTscReset() resets the TSC.  pentiumTscGet32() gets the lower half of the
64Bit TSC, and pentiumTscGet64() gets the entire 64Bit TSC.

Four other routines are provided in this library.  They are:
.CS
  void   pentiumTlbFlush (void)

  void   pentiumSerialize (void)

  STATUS pentiumBts
	 (
         char * pFlag                   /@ flag address @/
	 )

  STATUS pentiumBtc (pFlag)
	 (
         char * pFlag                   /@ flag address @/
	 )
.CE
pentiumTlbFlush() flushes TLBs (Translation Lookaside Buffers). 
pentiumSerialize() does serialization by executing CPUID instruction.
pentiumBts() executes an atomic compare-and-exchange instruction to set a bit.
pentiumBtc() executes an atomic compare-and-exchange instruction to clear a bit.


INTERNAL
Many routines in this module doesn't use the "c" frame pointer %ebp@ !
This is only for the benefit of the stacktrace facility to allow it 
to properly trace tasks executing within these routines.

SEE ALSO: 
.I "Pentium, PentiumPro Family Developer's Manual"
*/


#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "regs.h"
#include "arch/i86/pentiumLib.h"


        .data
	.globl  FUNC(copyright_wind_river)
	.long   FUNC(copyright_wind_river)


	/* internals */

	.globl	GTEXT(pentiumCr4Get)
	.globl	GTEXT(pentiumCr4Set)
	.globl	GTEXT(pentiumP6PmcStart)
	.globl	GTEXT(pentiumP6PmcStop)
	.globl	GTEXT(pentiumP6PmcStop1)
	.globl	GTEXT(pentiumP6PmcGet)
	.globl	GTEXT(pentiumP6PmcGet0)
	.globl	GTEXT(pentiumP6PmcGet1)
	.globl	GTEXT(pentiumP6PmcReset)
	.globl	GTEXT(pentiumP6PmcReset0)
	.globl	GTEXT(pentiumP6PmcReset1)
        .globl  GTEXT(pentiumP5PmcStart0)
        .globl  GTEXT(pentiumP5PmcStart1)
        .globl  GTEXT(pentiumP5PmcStop0)
        .globl  GTEXT(pentiumP5PmcStop1)
        .globl  GTEXT(pentiumP5PmcReset)
        .globl  GTEXT(pentiumP5PmcReset0)
        .globl  GTEXT(pentiumP5PmcReset1)
        .globl  GTEXT(pentiumP5PmcGet)
        .globl  GTEXT(pentiumP5PmcGet0)
        .globl  GTEXT(pentiumP5PmcGet1)
	.globl	GTEXT(pentiumTscGet64)
	.globl	GTEXT(pentiumTscGet32)
	.globl	GTEXT(pentiumTscReset)
	.globl	GTEXT(pentiumMsrGet)
	.globl	GTEXT(pentiumMsrSet)
	.globl	GTEXT(pentiumTlbFlush)
	.globl	GTEXT(pentiumSerialize)
	.globl	GTEXT(pentiumBts)
	.globl	GTEXT(pentiumBtc)


	.data
	.balign 16,0x90
_pmcBusy:
	.byte	0x00			/* PMC busy flag, 1 = busy */
_pmc0Busy:
        .byte   0x00                    /* PMC0 busy flag, 1 = busy */
_pmc1Busy:
        .byte   0x00                    /* PMC1 busy flag, 1 = busy */

	.text
	.balign 16,0x90

/*******************************************************************************
*
* pentiumCr4Get - get contents of CR4 register
*
* SYNOPSIS
* \ss
* int pentiumCr4Get (void)
* \se
*
* This routine gets the contents of the CR4 register.
*
* RETURNS: Contents of CR4 register.
*/

FUNC_LABEL(pentiumCr4Get)
	movl	%cr4,%eax
	ret

/*******************************************************************************
*
* pentiumCr4Set - sets specified value to the CR4 register
*
* SYNOPSIS
* \ss
* void pentiumCr4Set (cr4)
*    int cr4;		/@ value to write CR4 register @/
* \se
* This routine sets a specified value to the CR4 register.
*
*
* RETURNS: N/A
*/

	.balign 16,0x90
FUNC_LABEL(pentiumCr4Set)
	movl	SP_ARG1(%esp),%eax
	movl	%eax,%cr4
	ret

/*******************************************************************************
*
* pentiumP6PmcStart - start both PMC0 and PMC1
*
* SYNOPSIS
* \ss
* STATUS pentiumP6PmcStart (pmcEvtSel0, pmcEvtSel1)
*     int pmcEvtSel0;		/@ Performance Event Select Register 0 @/
*     int pmcEvtSel1;		/@ Performance Event Select Register 1 @/
* \se
* 
* This routine starts both PMC0 (Performance Monitoring Counter 0) and PMC1
* by writing specified events to Performance Event Select Registers. 
* The first parameter is a content of Performance Event Select Register 0,
* and the second parameter is for the Performance Event Select Register 1.
*
* RETURNS: OK or ERROR if PMC is already started.
*/

        .balign 16,0x90
FUNC_LABEL(pentiumP6PmcStart)
	xorl	%eax,%eax
	movl	$ TRUE, %edx
	lock				/* lock the BUS */
	cmpxchgb %dl,_pmcBusy		/* if (_pmcBusy == 0) */
	jnz	pentiumP6PmcStart0	/*   {ZF = 1; _pmcBusy = TRUE;} */

	movl	SP_ARG1(%esp),%eax	/* low-order 32 bits */
	xorl	%edx,%edx		/* high-order 32 bits */
	movl	$ MSR_EVNTSEL0,%ecx	/* specify MSR_EVNTSEL0 */
	wrmsr				/* write %edx:%eax to MSR_EVNTSEL0 */
	movl	SP_ARG2(%esp),%eax	/* low-order 32 bits */
	xorl	%edx,%edx		/* high-order 32 bits */
	movl	$ MSR_EVNTSEL1,%ecx	/* specify MSR_EVNTSEL1 */
	wrmsr				/* write %edx:%eax to MSR_EVNTSEL1 */
	xorl	%eax,%eax		/* return OK */
	ret

pentiumP6PmcStart0:
	movl	$ ERROR,%eax
	ret

/*******************************************************************************
*
* pentiumP6PmcStop - stop both PMC0 and PMC1
*
* SYNOPSIS
* \ss
* void pentiumP6PmcStop (void)
* \se
* 
* This routine stops both PMC0 (Performance Monitoring Counter 0) and PMC1
* by clearing two Performance Event Select Registers.
*
* RETURNS: N/A
*/

        .balign 16,0x90
FUNC_LABEL(pentiumP6PmcStop)
	xorl	%eax,%eax		/* zero low-order 32 bits */
	xorl	%edx,%edx		/* zero high-order 32 bits */
	movl	$ MSR_EVNTSEL0,%ecx	/* specify MSR_EVNTSEL0 */
	wrmsr				/* write %edx:%eax to MSR_EVNTSEL0 */
	movl	$ MSR_EVNTSEL1,%ecx	/* specify MSR_EVNTSEL1 */
	wrmsr				/* write %edx:%eax to MSR_EVNTSEL1 */

	movl	$ TRUE, %eax
	xorl	%edx,%edx
	lock				/* lock the BUS */