vxshow.c

VXWORKS源代码

			break; 

		    case 4: 
			printf (" Genuine Intel486(TM) CPU"); 
			break; 

		    case 5: 
			printf (" Genuine IntelSX2(TM) CPU"); 
			break; 

		    case 7: 
			printf (" Genuine WriteBack Enhanced IntelDX2(TM) CPU");
			break; 

		    case 8: 
			printf (" Genuine IntelDX4(TM) CPU"); 
			break; 

		    default: 
			printf (" Genuine Intel486(TM) CPU"); 
		    }
	        } 
	    else if (cpu_type == 5) 
		printf (" Genuine Intel Pentium(R) CPU"); 
	    else if ((cpu_type == 6) && (((cpu_signature >> 4) & 0xf) == 1)) 
		printf (" Genuine Intel Pentium(R) Pro CPU"); 
	    else if ((cpu_type == 6) && (((cpu_signature >> 4) & 0xf) == 3)) 
		printf (" Genuine Intel Pentium(R) II CPU, model 3"); 
	    else if (((cpu_type == 6) && (((cpu_signature >> 4) & 0xf) == 5)) ||
		     ((cpu_type == 6) && (((cpu_signature >> 4) & 0xf) == 7)))
		{ 
		celeron_flag = 0; 
		pentiumxeon_flag = 0; 
		cache_temp = cache_eax & 0xFF000000; 
		if (cache_temp == 0x40000000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x44000000) && (cache_temp <= 0x45000000)) 
		    pentiumxeon_flag = 1; 
	
		cache_temp = cache_eax & 0xFF0000; 
		if (cache_temp == 0x400000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x440000) && (cache_temp <= 0x450000)) 
		    pentiumxeon_flag = 1;

		cache_temp = cache_eax & 0xFF00; 
		if (cache_temp == 0x4000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x4400) && (cache_temp <= 0x4500))
		    pentiumxeon_flag = 1; 

		cache_temp = cache_ebx & 0xFF000000; 
		if (cache_temp == 0x40000000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x44000000) && (cache_temp <= 0x45000000)) 
		    pentiumxeon_flag = 1; 

		cache_temp = cache_ebx & 0xFF0000; 
		if (cache_temp == 0x400000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x440000) && (cache_temp <= 0x450000)) 
		    pentiumxeon_flag = 1;

		cache_temp = cache_ebx & 0xFF00; 
		if (cache_temp == 0x4000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x4400) && (cache_temp <= 0x4500)) 
		    pentiumxeon_flag = 1; 

		cache_temp = cache_ebx & 0xFF; 
		if (cache_temp == 0x40) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x44) && (cache_temp <= 0x45)) 
		    pentiumxeon_flag = 1;

		cache_temp = cache_ecx & 0xFF000000; 
		if (cache_temp == 0x40000000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x44000000) && (cache_temp <= 0x45000000)) 
		    pentiumxeon_flag = 1; 
	
		cache_temp = cache_ecx & 0xFF0000; 
		if (cache_temp == 0x400000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x440000) && (cache_temp <= 0x450000)) 
		    pentiumxeon_flag = 1;

		cache_temp = cache_ecx & 0xFF00; 
		if (cache_temp == 0x4000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x4400) && (cache_temp <= 0x4500)) 
		    pentiumxeon_flag = 1; 

		cache_temp = cache_ecx & 0xFF; 
		if (cache_temp == 0x40) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x44) && (cache_temp <= 0x45)) 
		    pentiumxeon_flag = 1;

		cache_temp = cache_edx & 0xFF000000; 
		if (cache_temp == 0x40000000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x44000000) && (cache_temp <= 0x45000000)) 
		    pentiumxeon_flag = 1;

		cache_temp = cache_edx & 0xFF0000; 
		if (cache_temp == 0x400000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x440000) && (cache_temp <= 0x450000)) 
		    pentiumxeon_flag = 1; 

		cache_temp = cache_edx & 0xFF00; 
		if (cache_temp == 0x4000) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x4400) && (cache_temp <= 0x4500)) 
		    pentiumxeon_flag = 1; 

		cache_temp = cache_edx & 0xFF; 
		if (cache_temp == 0x40) 
		    celeron_flag = 1; 
		if ((cache_temp >= 0x44) && (cache_temp <= 0x45)) 
		    pentiumxeon_flag = 1;

		if (celeron_flag == 1) 
		    printf (" Genuine Intel Celeron(R) CPU, model 5"); 
		else 
		    { 
		    if (pentiumxeon_flag == 1) 
		        { 
			printf (" Genuine Intel Pentium(R) "); 
			if (((cpu_signature >> 4) & 0x0f) == 5) 
			    printf ("II Xeon(TM) CPU"); 
			else 
			    printf ("III Xeon(TM) CPU");
			printf (" model 7");
		        } 
		    else 
		        { 
			if (((cpu_signature >> 4) & 0x0f) == 5)
			    { 
			    printf (" Genuine Intel Pentium(R) II CPU, "); 
			    printf ("model 5 or Intel Pentium(R) II Xeon(TM)");
			    printf (" CPU");
			    } 
			else 
			    { 
			    printf (" Genuine Intel Pentium(R) III CPU, ");
			    printf ("model 7 or Intel Pentium(R) III Xeon(TM)");
			    printf (" CPU, model 7");
			    }
		        }
		    }
	        }
	    else if ((cpu_type == 6) && (((cpu_signature >> 4) & 0xf) == 6))
		printf (" Genuine Intel Celeron(R) CPU, model 6");
	    else if ((features_ebx & 0xff) != 0) 
		{
		while ((brand_index < BRAND_TABLE_SIZE) &&
		       ((features_ebx & 0xff) != 
				       brand_table[brand_index].brand_value))
		    brand_index++;
		if (brand_index < BRAND_TABLE_SIZE)
		    {
		    if ((cpu_signature == 0x6B1) &&
		        (brand_table[brand_index].brand_value == 0x3))
			printf (" Genuine Intel Celeron(R) CPU");
		    else
		        printf ("%s", brand_table[brand_index].brand_string);
		    }
		else
		    printf ("n unknown Genuine Intel CPU"); 
		}
	    else 
		printf ("n unknown Genuine Intel CPU"); 

	    printf ("\nProcessor Family: %X", cpu_type);
	    if (cpu_type == 0xf)
		printf ("\n Extended Family: %x",(cpu_signature >> 20) & 0xff);
	    printf ("\nModel: %X", (cpu_signature>>4) & 0xf); 
	    if (((cpu_signature >> 4) & 0xf) == 0xf)
		printf ("\n Extended Model: %x", (cpu_signature >> 16) & 0xf);
	    printf ("\nStepping: %X\n", cpu_signature & 0xf); 

	    if (cpu_signature & 0x1000) 
		printf ("\nThe CPU is an OverDrive(R) CPU"); 
	    else if (cpu_signature & 0x2000) 
		printf ("\nThe CPU is the upgrade CPU in a dual CPU system"); 
	    if (features_edx & FPU_FLAG) 
		printf ("\nThe CPU contains an on-chip FPU"); 
	    if (features_edx & VME_FLAG) 
		printf ("\nThe CPU supports Virtual Mode Extensions");
	    if (features_edx & DE_FLAG) 
		printf ("\nThe CPU supports the Debugging Extensions"); 
	    if (features_edx & PSE_FLAG) 
		printf ("\nThe CPU supports Page Size Extensions"); 
	    if (features_edx & TSC_FLAG) 
		printf ("\nThe CPU supports Time Stamp Counter"); 
	    if (features_edx & MSR_FLAG) 
		printf ("\nThe CPU supports Model Specific Registers"); 
	    if (features_edx & PAE_FLAG) 
		printf ("\nThe CPU supports Physical Address Extension");
	    if (features_edx & MCE_FLAG) 
		printf ("\nThe CPU supports Machine Check Exceptions");
	    if (features_edx & CX8_FLAG) 
		printf ("\nThe CPU supports the CMPXCHG8B instruction");
	    if (features_edx & APIC_FLAG)
		printf ("\nThe CPU contains an on-chip APIC");
	    if (features_edx & SEP_FLAG)
	        { 
		if ((cpu_type == 6) && ((cpu_signature & 0xff) < 0x33))
		    printf ("\nThe CPU does not support the Fast System Call");
		else 
		    {
#if	FALSE	/* no system call in T2.2 */
    		    long long sysenterCs;
    		    long long sysenterEsp;
    		    long long sysenterEip;

		    printf ("\nThe CPU supports the Fast System Call");
		    pentiumMsrGet (MSR_SYSENTER_CS, &sysenterCs);
		    pentiumMsrGet (MSR_SYSENTER_ESP, &sysenterEsp);
		    pentiumMsrGet (MSR_SYSENTER_EIP, &sysenterEip);
		    printf (":  CS=0x%x, ESP=0x%x, EIP=0x%x", (int)sysenterCs,
			    (int)sysenterEsp, (int)sysenterEip);
#else
		    printf ("\nThe CPU supports the Fast System Call");
#endif	/* FALSE */
		    }
	        }
	    if (features_edx & MTRR_FLAG) 
		printf ("\nThe CPU supports the Memory Type Range Registers"); 
	    if (features_edx & PGE_FLAG) 
		printf ("\nThe CPU supports Page Global Enable"); 
	    if (features_edx & MCA_FLAG) 
		printf ("\nThe CPU supports the Machine Check Architecture");
	    if (features_edx & CMOV_FLAG) 
		printf ("\nThe CPU supports the Conditional Move Instruction");
	    if (features_edx & PAT_FLAG)
		printf ("\nThe CPU supports the Page Attribute Table");
	    if (features_edx & PSE36_FLAG)
		printf ("\nThe CPU supports 36-bit Page Size Extension");
	    if (features_edx & PSNUM_FLAG)
		printf ("\nThe CPU supports the CPU serial number");
	    if (features_edx & CLFLUSH_FLAG)
		printf ("\nThe CPU supports the CLFLUSH instruction");
	    if (features_edx & DTS_FLAG)
		printf ("\nThe CPU supports the Debug Trace Store feature");
	    if (features_edx & ACPI_FLAG)
		printf ("\nThe CPU supports ACPI registers in MSR space");
	    if (features_edx & MMX_FLAG)
		printf ("\nThe CPU supports Intel Architecture MMX(TM)");
	    if (features_edx & FXSR_FLAG)
		printf ("\nThe CPU supports the Fast FPP save and restore");
	    if (features_edx & SSE_FLAG)
		printf ("\nThe CPU supports the Streaming SIMD Extensions");
	    if (features_edx & SSE2_FLAG)
		printf ("\nThe CPU supports the Streaming SIMD Extensions 2");
	    if (features_edx & SS_FLAG)
		printf ("\nThe CPU supports Self-Snoop");
	    if ((features_edx & HTT_FLAG) && 
		(((features_ebx >> 16) & 0x0FF) > 1))
		printf ("\nThe CPU supports the Hyper-Threading Technology");
	    if (features_edx & TM_FLAG)
		printf ("\nThe CPU supports the Thermal Monitor");
	    }
	else 
	    { 
	    printf ("t least an 80486 CPU. \n"); 
	    printf ("It does not contain a Genuine Intel part and\n");
	    printf ("as a result, the CPUID detection information\n"); 
	    printf ("cannot be determined at this time.");
	    }
        }
    printf ("\n");
    }

/*******************************************************************************
*
* vxDrShow - show content of the Debug Registers 0 to 7
*
* This routine prints the contents of the Debug Registers 0 to 7 (DR0
* through DR7) to the standard output device.  The displayed register
* context is not associated with any particular task context, as this
* routine will simply fetch the current content of each physical debug
* register when it is called.
*
* Note that debug registers DR4 and DR5 are reserved when debug extensions
* are enabled (when the DE flag in control register CR4 is set), and
* attempts to reference the DR4 and DR5 registers cause an invalid-opcode
* exception to be generated.  When debug extensions are not enabled (when
* the DE flag is clear), these registers are aliased to debug registers
* DR6 and DR7.
*
* RETURNS: N/A
*/

void vxDrShow (void)
    {
    int dreg[8];			/* debug registers */

    vxDrGet (&dreg[0], &dreg[1], &dreg[2], &dreg[3],
    	     &dreg[4], &dreg[5], &dreg[6], &dreg[7]);

    printf (dregFmt, dreg[0], dreg[1], dreg[2], dreg[3],
    		     dreg[4], dreg[5], dreg[6], dreg[7]);
    }

/*******************************************************************************
*
* vxSseShow - print the contents of a task's SIMD registers
*
* This routine prints the contents of a task's Streaming SIMD
* Extension (SSE) register context, if any, to the standard output
* device.
*
* RETURNS: N/A
*/

void vxSseShow
    (
    int taskId          /* ID of task to display SSE registers for */
    )
    {
    const int features_edx = sysCpuId.featuresEdx;


    if ((features_edx & SSE_FLAG) || (features_edx & SSE2_FLAG))
        {
        const FP_CONTEXT *     pFpContext;

        const WIND_TCB * const pTcb = taskTcb (taskId);


        if ((pTcb != NULL) && ((pFpContext = pTcb->pFpContext) != NULL))
            {
            const FPX_CONTEXT * const pFpxContext = &(pFpContext->u.x);

            const UINT32 * pInt = (UINT32 *) &(pFpxContext->xmm[0]);
            printf ("\nxmm0   = %08x_%08x_%08x_%08x\n",
                    pInt[3], pInt[2], pInt[1], pInt[0]);

            pInt = (UINT32 *) &(pFpxContext->xmm[1]);
            printf ("xmm1   = %08x_%08x_%08x_%08x\n",
                    pInt[3], pInt[2], pInt[1], pInt[0]);

            pInt = (UINT32 *) &(pFpxContext->xmm[2]);
            printf ("xmm2   = %08x_%08x_%08x_%08x\n",
                    pInt[3], pInt[2], pInt[1], pInt[0]);

            pInt = (UINT32 *) &(pFpxContext->xmm[3]);
            printf ("xmm3   = %08x_%08x_%08x_%08x\n",
                    pInt[3], pInt[2], pInt[1], pInt[0]);

            pInt = (UINT32 *) &(pFpxContext->xmm[4]);
            printf ("xmm4   = %08x_%08x_%08x_%08x\n",
                    pInt[3], pInt[2], pInt[1], pInt[0]);

            pInt = (UINT32 *) &(pFpxContext->xmm[5]);
            printf ("xmm5   = %08x_%08x_%08x_%08x\n",
                    pInt[3], pInt[2], pInt[1], pInt[0]);

            pInt = (UINT32 *) &(pFpxContext->xmm[6]);
            printf ("xmm6   = %08x_%08x_%08x_%08x\n",
                    pInt[3], pInt[2], pInt[1], pInt[0]);

            pInt = (UINT32 *) &(pFpxContext->xmm[7]);
            printf ("xmm7   = %08x_%08x_%08x_%08x\n",
                    pInt[3], pInt[2], pInt[1], pInt[0]);

            return;
            }

        printf ("\ntask does not have SIMD context\n");
        return;
        }

    printf ("\nCPU does not support SIMD\n");
    }