vxshow.c

VXWORKS源代码

/* vxShow.c - Intel Architecture processor show routines */

/* Copyright 1984-2002 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01g,12mar02,pai  Add an initialization routine for configuring the show
                 routines into a build configuration (SPR 74103).  Added
                 vxSseShow() routine and updated documentation.
01f,07mar02,hdn  updated with AP485 rev-019 for HTT (spr 73359)
01e,20nov01,hdn  doc clean up for 5.5
01d,07nov01,hdn  added header file vxI86Lib.h to shut off the warning
01c,01nov01,hdn  added vxDrShow() to see the debug registers
01b,11oct01,hdn  uncommented out the "Fast System Call" printing
01a,14aug01,hdn  taken from T31 ver 01h, added PENTIUM4 support
*/

/*
DESCRIPTION
This library contains routines for printing various types of information
on Intel Architecture CPUs.

To use these routines, install the library using the vxShowInit()
routine, which is called automatically when either of the following
configuration methods is employed:

.iP
INCLUDE_SHOW_ROUTINES is defined in a BSP config.h file for
command-line builds.

.iP
The INCLUDE_SHOW_ROUTINES Component is selected for Tornado
Project Facility builds.
.LP

Included in this library is a routine for reporting details on Intel
Architecture 80x86 and Pentium generation processors and coprocessors.
This vxCpuShow() routine is essentially a VxWorks implementation of the
code found in the Intel Application Note, "AP-485, Intel Processor
Identification and the CPUID Instruction".  The vxCpuShow() routine may
be useful for determining specific features found on the target processor
upon which VxWorks is running.

In addition to the vxCpuShow() routine, there are routines for showing
processer register contents.  Some of these routines show certain processor
registers independent of any task context, while others show register
values associated with a particular task context.

There is a simple routine for showing the contents of the processor debug
registers.  The debug registers (DR0 through DR7) control, and allow
monitoring of, the processor's debugging operations.

This library provides a routine for showing a task's optional Streaming
SIMD Extension (SSE) register context.  Target-based task information
routines, such as ti(), will display a task's SSE context, if any, when
this library is built into a VxWorks system.

SEE ALSO:
.pG "Configuration"
*/


/* includes */

#include "vxWorks.h"
#include "regs.h"
#include "vxLib.h"
#include "stdio.h"
#include "string.h"
#include "taskLib.h"
#include "fioLib.h"
#include "fppLib.h"
#include "arch/i86/pentiumLib.h"
#include "private/funcBindP.h"


/* defines */

#define FPU_FLAG	0x00000001	/* floating point unit on chip */
#define VME_FLAG 	0x00000002	/* virtual mode extension */
#define DE_FLAG 	0x00000004	/* debugging extension */
#define PSE_FLAG 	0x00000008	/* page size extension */
#define TSC_FLAG 	0x00000010	/* time stamp counter */
#define MSR_FLAG 	0x00000020	/* model specific register */
#define PAE_FLAG 	0x00000040	/* physical address extension */
#define MCE_FLAG 	0x00000080	/* machine check exception */
#define CX8_FLAG 	0x00000100	/* CMPXCHG8 instruction supported */
#define APIC_FLAG 	0x00000200	/* on-chip APIC hardware support */
#define SEP_FLAG 	0x00000800	/* fast system call */
#define MTRR_FLAG 	0x00001000	/* memory type range registers */
#define PGE_FLAG 	0x00002000	/* page global enable */
#define MCA_FLAG 	0x00004000	/* machine check architecture */
#define CMOV_FLAG 	0x00008000	/* conditional move instruction */
#define PAT_FLAG 	0x00010000	/* page attribute table */
#define PSE36_FLAG 	0x00020000	/* 36-bit page size extension */
#define PSNUM_FLAG 	0x00040000	/* processor serial no is enabled */
#define CLFLUSH_FLAG 	0x00080000	/* CLFLUSH instruction supported */
#define DTS_FLAG 	0x00200000	/* Debug Trace Store */
#define ACPI_FLAG 	0x00400000	/* ACPI registers in MSR space */
#define MMX_FLAG 	0x00800000	/* IA MMX technology supported */
#define FXSR_FLAG 	0x01000000	/* fast floating point save, restore */
#define SSE_FLAG 	0x02000000	/* Streaming SIMD Extension */
#define SSE2_FLAG 	0x04000000	/* Streaming SIMD Extension 2 */
#define SS_FLAG 	0x08000000	/* Self Snoop */
#define TM_FLAG 	0x20000000	/* Thermal Monitor */
#define HTT_FLAG 	0x10000000	/* Hyper Threading Technology */

#define BRAND_TABLE_SIZE	10	/* brand table size */

typedef struct brand_entry		/* brand table entry */
	{
	long brand_value;		/* brand id */
	char * brand_string;		/* corresponding brand name */
	} BRAND_ENTRY;


/* externals */

IMPORT CPUID	sysCpuId;
IMPORT int	sysProcessor;
IMPORT int	sysCoprocessor;


/* locals */

#if	FALSE	/* Unlike AE, 5.5 does not have TSS per task */

LOCAL const char * tssFmt0 = "\n\
link : 0x%08x\n\
esp0 : 0x%08x   ss0 : 0x%08x\n\
esp1 : 0x%08x   ss1 : 0x%08x\n\
esp2 : 0x%08x   ss2 : 0x%08x\n\
 cr3 : 0x%08x   eip : 0x%08x eflags : 0x%08x\n\
 eax : 0x%08x   ecx : 0x%08x    edx : 0x%08x    ebx : 0x%08x\n\
 esp : 0x%08x   ebp : 0x%08x    esi : 0x%08x    edi : 0x%08x\n\
  cs : 0x%08x    ds : 0x%08x     ss : 0x%08x\n\
  es : 0x%08x    fs : 0x%08x     gs : 0x%08x\n\
 ldt : 0x%08x tflag : 0x%08x iomapb : 0x%08x\n";

#endif

LOCAL char intelId[] = "GenuineIntel";

LOCAL BRAND_ENTRY brand_table [BRAND_TABLE_SIZE] =
	{
	{0x01, " Genuine Intel Celeron(R) CPU"},
	{0x02, " Genuine Intel Pentium(R) III CPU"},
	{0x03, " Genuine Intel Pentium(R) III Xeon(TM) CPU"},
	{0x04, " Genuine Intel Pentium(R) III CPU"},
	{0x06, " Genuine Mobile Intel Pentium(R) III CPU-M"},
	{0x07, " Genuine Mobile Intel Celeron(R) CPU"},
	{0x08, " Genuine Intel Pentium(R) 4 CPU"},
	{0x09, " Genuine Intel Pentium(R) 4 CPU"},
	{0x0B, " Genuine Intel Xeon(TM) CPU"},
	{0x0E, " Genuine Intel Xeon(TM) CPU"}
	};

LOCAL const char * const dregFmt = "\n\
dr0 : 0x%08x   dr1 : 0x%08x    dr2 : 0x%08x    dr3 : 0x%08x\n\
dr4 : 0x%08x   dr5 : 0x%08x    dr6 : 0x%08x    dr7 : 0x%08x\n";


/* forward declarations */

void vxCpuShow (void);
void vxDrShow (void);
void vxSseShow (int);



/*******************************************************************************
*
* vxShowInit - initialize the Intel 80x86 and Pentium show routines
*
* This routine links Intel 80x86 and Pentium family show routines into
* the VxWorks system.  It is called automatically when the show facility
* is configured into VxWorks using either of the following methods:
*
* .iP
* INCLUDE_SHOW_ROUTINES is defined in a BSP config.h file for
* command-line builds.
*
* .iP
* The INCLUDE_SHOW_ROUTINES Component is selected for Tornado
* Project Facility builds.
* .LP
*
* INTERNAL
* This routine could be called before the RTOS is fully initialized.  The
* routine is used primarilly as a linkage symbol to pull the library into
* a build.  Other initialization should be very simple.  For example, set
* the initial values for file-scope and global variables.  Do not try to
* allocate memory in this routine.  Do not call VxWorks kernel routines.
*
* The <sysCpuId> structure is populated by calling sysCpuProbe().  Thus,
* sysCpuProbe() must be called if there is to be any hope of correctly
* determining whether to bind <_func_sseTaskRegsShow> to the SSE show
* routine.
*
* RETURNS: N/A
*/

void vxShowInit (void)
    {
    const int features_edx = sysCpuId.featuresEdx;

    /* Bind the Streaming SIMD register show routine ? */

    if ((features_edx & SSE_FLAG) || (features_edx & SSE2_FLAG))
        {
        _func_sseTaskRegsShow = (FUNCPTR) vxSseShow;
        }
    }

#if	FALSE	/* Unlike AE, 5.5 does not have TSS per task */

/*******************************************************************************
*
* vxTssShow - show content of the TSS (Task State Segment)
*
* This routine shows content of the TSS (Task State Segment)
*
* RETURNS: N/A
*
* NOMANUAL
*/

void vxTssShow
    (
    int  tid                    	/* task ID of task */
    )
    {
    WIND_TCB * pTcb;			/* pointer to TCB */
    TSS * pTss;				/* pointer to TSS */

    if (tid == 0)
	pTcb = taskIdCurrent;
    else
	pTcb = (WIND_TCB *) tid;

    pTss = pTcb->tss;			/* get the address of TSS */

    printf (tssFmt0,     pTss->link,   pTss->esp0,  pTss->ss0,
	    pTss->esp1,  pTss->ss1,    pTss->esp2,  pTss->ss2,
	    pTss->cr3,   pTss->eip,    pTss->eflags,
	    pTss->eax,   pTss->ecx,    pTss->edx,   pTss->ebx,
	    pTss->esp,   pTss->ebp,    pTss->esi,   pTss->edi,
	    pTss->cs,    pTss->ds,     pTss->ss,
	    pTss->es,    pTss->fs,     pTss->gs,
	    pTss->ldt,   pTss->tflag,  pTss->iomapb);
    }

#endif

/*******************************************************************************
*
* vxCpuShow - show CPU type, family, model, and supported features.
*
* This routine prints information on Intel Architecture processors
* and coprocessors, including CPU type, family, model, and supported
* features.
*
* INTERNAL
* This source code came from Intel AP-485 and kept as is for ease of
* future upgrade / maintenance.
*
* RETURNS: N/A
*/

void vxCpuShow (void)
    {
    char cpu_type	= (sysCpuId.signature & CPUID_FAMILY) >> 8; 
    char fpu_type	= 0;
    int  cpu_signature	= sysCpuId.signature; 
    int  features_ebx	= sysCpuId.featuresEbx;
#if	FALSE
    int  features_ecx	= sysCpuId.featuresEcx;
#endif	/* FALSE */
    int  features_edx	= sysCpuId.featuresEdx;
    int  cache_eax	= sysCpuId.cacheEax;  
    int  cache_ebx	= sysCpuId.cacheEbx;
    int  cache_ecx	= sysCpuId.cacheEcx;
    int  cache_edx	= sysCpuId.cacheEdx;
    char cpuid_flag	= (sysCpuId.highestValue != 0); 
    char intel_CPU	= FALSE; 
    char vendor_id[12]; 
    int  cache_temp; 
    int  celeron_flag;
    int  pentiumxeon_flag;
    char brand_string[48];
    int	 brand_index	= 0;


    if (sysProcessor == NONE)
        {
	printf ("sysCpuProbe() is not executed.\n");
	return;
	}

    if ((sysCoprocessor == X86FPU_387) || (sysCoprocessor == X86FPU_487))
        fpu_type = 3;

    bcopy ((char *)sysCpuId.vendorId, vendor_id, sizeof (vendor_id));
    bcopy ((char *)sysCpuId.brandString, brand_string, sizeof (brand_string));

    if (strncmp (intelId, (char *)sysCpuId.vendorId, sizeof (vendor_id)) == 0)
	intel_CPU = TRUE;

    printf ("This system has a"); 
    if (cpuid_flag == 0) 
        {
	switch (cpu_type) 
	    { 
#if	FALSE
	    case 0: 
		printf ("n 8086/8088 CPU"); 
		if (fpu_type) 
		    printf (" and an 8087 math coCPU"); 
		break; 

	    case 2: 
		printf ("n 80286 CPU"); 
		if (fpu_type) 
		    printf (" and an 80287 math coCPU"); 
		break; 
#endif	/* FALSE */

	    case 3: 
		printf ("n 80386 CPU"); 
		if (fpu_type == 2) 
		    printf (" and an 80287 math coCPU"); 
		else if (fpu_type) 
		    printf (" and an 80387 math coCPU"); 
		break; 

	    case 4: 
		if (fpu_type) 
		    printf ("n 80486DX, 80486DX2 CPU or 80487SX math coCPU"); 
		else 
		    printf ("n 80486SX CPU"); 
		break; 

	    default: 
		printf ("n unknown CPU"); 
	    }
        } 
    else 
        { 

	/* using cpuid instruction */ 

	if (brand_string[0])
	    {
	    brand_index = 0;
	    while ((brand_string[brand_index] == ' ') && (brand_index < 48))
		brand_index++;		/* remove leading Space */
	    if (brand_index != 48)
		printf ("%s", &brand_string[brand_index]);
	    }

	if (intel_CPU) 
	    { 
	    if (cpu_type == 4) 
	        { 
		switch ((cpu_signature >> 4) & 0xf) 
		    { 
		    case 0: 
		    case 1: 
			printf (" Genuine Intel486(TM) DX CPU");
		        break; 

		    case 2: 
			printf (" Genuine Intel486(TM) SX CPU"); 
			break; 

		    case 3: 
			printf (" Genuine IntelDX2(TM) CPU");