pentiumlib.c

VXWORKS源代码

* \se
*
* This routine stops only PMC0 (Performance Monitoring Counter 0)
* by clearing the PMC0 bits of Control and Event Select Register.
*
* RETURNS: N/A
*/
void pentiumPmcStop0 (void)
    {
    if ((sysCpuId.featuresEdx & CPUID_MSR) && (sysProcessor == X86CPU_PENTIUM))
        pentiumP5PmcStop0();
    }

/*******************************************************************************
*
* pentiumPmcStop1 - stop PMC1
*
* SYNOPSIS
* \ss
* void pentiumPmcStop1 (void)
* \se
*
* This routine stops only PMC1 (Performance Monitoring Counter 1)
* by clearing the PMC1 bits of Control and Event Select Register.
*
* RETURNS: N/A
*/
void pentiumPmcStop1 (void)
    {
    if (sysCpuId.featuresEdx & CPUID_MSR)
        {
        if (sysProcessor == X86CPU_PENTIUM)
            pentiumP5PmcStop1();
        else if (sysProcessor == X86CPU_PENTIUMPRO)
            pentiumP6PmcStop1();
        }
    }

/*******************************************************************************
*
* pentiumPmcGet - get the contents of PMC0 and PMC1
*
* SYNOPSIS
* \ss
* void pentiumPmcGet (pPmc0, pPmc1)
*     long long int * pPmc0;            /@ Performance Monitoring Counter 0 @/
*     long long int * pPmc1;            /@ Performance Monitoring Counter 1 @/
* \se
*
* This routine gets the contents of both PMC0 (Performance Monitoring Counter 0)
* and PMC1.  The first parameter is a pointer of 64Bit variable to store
* the content of the Counter 0, and the second parameter is for the Counter 1.
*
* RETURNS: N/A
*/
void pentiumPmcGet
    (
    long long int * pPmc0, 
    long long int * pPmc1
    )
    {
    if (sysCpuId.featuresEdx & CPUID_MSR)
        {
        if (sysProcessor == X86CPU_PENTIUM)
            pentiumP5PmcGet(pPmc0, pPmc1);
        else if (sysProcessor == X86CPU_PENTIUMPRO)
            pentiumP6PmcGet(pPmc0, pPmc1);
        }
    }

/*******************************************************************************
*
* pentiumPmcGet0 - get the contents of PMC0
*
* SYNOPSIS
* \ss
* void pentiumPmcGet0 (pPmc0)
*     long long int * pPmc0;            /@ Performance Monitoring Counter 0 @/
* \se
*
* This routine gets the contents of PMC0 (Performance Monitoring Counter 0).
* The parameter is a pointer of 64Bit variable to store the content of
* the Counter.
*
* RETURNS: N/A
*/
void pentiumPmcGet0
    (
    long long int * pPmc0
    )
    {
    if (sysCpuId.featuresEdx & CPUID_MSR)
        {
        if (sysProcessor == X86CPU_PENTIUM)
            pentiumP5PmcGet0(pPmc0);
        else if (sysProcessor == X86CPU_PENTIUMPRO)
            pentiumP6PmcGet0(pPmc0);
        }
    }

/*******************************************************************************
*
* pentiumPmcGet1 - get the contents of PMC1
*
* SYNOPSIS
* \ss
* void pentiumPmcGet1 (pPmc1)
*     long long int * pPmc1;            /@ Performance Monitoring Counter 1 @/
* \se
*
* This routine gets a content of PMC1 (Performance Monitoring Counter 1).
* Parameter is a pointer of 64Bit variable to store the content of the Counter.
*
* RETURNS: N/A
*/
void pentiumPmcGet1
    (
    long long int * pPmc1
    )
    {
    if (sysCpuId.featuresEdx & CPUID_MSR)
        {
        if (sysProcessor == X86CPU_PENTIUM)
            pentiumP5PmcGet1(pPmc1);
        else if (sysProcessor == X86CPU_PENTIUMPRO)
            pentiumP6PmcGet1(pPmc1);
        }
    }
    
/*******************************************************************************
*
* pentiumPmcReset - reset both PMC0 and PMC1
*
* SYNOPSIS
* \ss
* void pentiumPmcReset (void)
* \se
* 
* This routine resets both PMC0 (Performance Monitoring Counter 0) and PMC1.
*
* RETURNS: N/A
*/
void pentiumPmcReset (void)
    {
    if (sysCpuId.featuresEdx & CPUID_MSR)
        {
        if (sysProcessor == X86CPU_PENTIUM)
            pentiumP5PmcReset();
        else if (sysProcessor == X86CPU_PENTIUMPRO)
            pentiumP6PmcReset();
        }
    }

/*******************************************************************************
*
* pentiumPmcReset0 - reset PMC0
*
* SYNOPSIS
* \ss
* void pentiumPmcReset0 (void)
* \se
*
* This routine resets PMC0 (Performance Monitoring Counter 0).
*
* RETURNS: N/A 
*/
void pentiumPmcReset0 (void)
    {
    if (sysCpuId.featuresEdx & CPUID_MSR)
        {
        if (sysProcessor == X86CPU_PENTIUM)
            pentiumP5PmcReset0();
        else if (sysProcessor == X86CPU_PENTIUMPRO)
            pentiumP6PmcReset0();
        }
    }

/*******************************************************************************
*
* pentiumPmcReset1 - reset PMC1
*
* SYNOPSIS
* \ss
* void pentiumPmcReset1 (void)
* \se
*
* This routine resets PMC1 (Performance Monitoring Counter 1).
*
* RETURNS: N/A
*/
void pentiumPmcReset1 (void)
    {
    if (sysCpuId.featuresEdx & CPUID_MSR)
        {
        if (sysProcessor == X86CPU_PENTIUM)
            pentiumP5PmcReset1();
        else if (sysProcessor == X86CPU_PENTIUMPRO)
            pentiumP6PmcReset1();
        }
    }

/*******************************************************************************
*
* pentiumMsrInit - initialize all the MSRs (Model Specific Register)
*
* This routine initializes all the MSRs in the processor.
* This routine works on either P5, P6 or P7 family processors.
*
* RETURNS: OK, or ERROR if RDMSR/WRMSR instructions are not supported.
*/

STATUS pentiumMsrInit (void)
    {
    PENTIUM_MSR * pMsr;		/* pointer to the MSR table */
    UINT32 value[2] = {0,0};
    UINT32 zero[2]  = {0,0};
    int ix;

    /* just return if RDMSR and WRMSR instruction are not supported */

    if ((sysCpuId.featuresEdx & CPUID_MSR) == 0)
	return (ERROR);

    switch (sysProcessor)
	{
	case X86CPU_PENTIUM:
	    pMsr = pentiumMsrP5;
    	    for (ix = 0; ix < pentiumMsrP5NumEnt; ix++, pMsr++)
	        {
	        switch (pMsr->addr)
	            {
	            case MSR_P5_MC_ADDR:	/* disable the MCA */
		        pentiumMcaEnable (FALSE);
	                break;

	            case MSR_CESR:		/* disable the PM */
	                pentiumMsrSet (pMsr->addr, (LL_INT *)&zero);
	                break;

	            default:
	                break;
	            }
	        }
	    break;

	case X86CPU_PENTIUMPRO:			/* PENTIUM[23] */
	    pMsr = pentiumMsrP6;
    	    for (ix = 0; ix < pentiumMsrP6NumEnt; ix++, pMsr++)
	        {
	        switch (pMsr->addr)
	            {
	            case MSR_APICBASE:		/* don't touch */
		        /* bit-11 can't be re-enabled except by hard reset */
	                break;

	            case MSR_ROB_CR_BKUPTMPDR6:	/* set the default value */
	                pentiumMsrGet (pMsr->addr, (LL_INT *)&value);
	  	        value[0] = MSR_ROB_CR_BKUPTMPDR6_DEFAULT;
	                pentiumMsrSet (pMsr->addr, (LL_INT *)&value);
	                break;

	            case MSR_MCG_CAP:		/* disable the MCA */
		        pentiumMcaEnable (FALSE);
	                break;

	            case MSR_DEBUGCTLMSR:	/* disable the debug features */
	            case MSR_EVNTSEL0:		/* disable the PM */
	            case MSR_EVNTSEL1:		/* disable the PM */
	            case MSR_PERFCTR0:		/* disable the PM */
	            case MSR_PERFCTR1:		/* disable the PM */
	                pentiumMsrSet (pMsr->addr, (LL_INT *)&zero);
	                break;

	            default:
	                break;
	            }
	        }
	    break;

	case X86CPU_PENTIUM4:
	    pMsr = pentiumMsrP7;
    	    for (ix = 0; ix < pentiumMsrP7NumEnt; ix++, pMsr++)
	        {
	        switch (pMsr->addr)
	            {
	            case IA32_APIC_BASE:	/* don't touch */
		        /* bit-11 can't be re-enabled except by hard reset */
	                break;

	            case IA32_MISC_ENABLE:	/* set the default value */
	                pentiumMsrGet (pMsr->addr, (LL_INT *)&value);
	  	        value[0] = IA32_MISC_ENABLE_DEFAULT;
	                pentiumMsrSet (pMsr->addr, (LL_INT *)&value);
	                break;

	            case IA32_MCG_CAP:		/* disable the MCA */
		        pentiumMcaEnable (FALSE);
	                break;

	            case IA32_MISC_CTL:		/* disable the serial number */
	            case IA32_THERM_INTERRUPT:	/* disable the thermal int. */
	            case IA32_DEBUGCTL:		/* disable the debug features */
	            case MSR_TC_PRECISE_EVENT:	/* disable the FE tagging */
	            case IA32_PEBS_ENABLE:	/* disable the PEBS */
	            case MSR_BPU_CCCR0:		/* disable the PM */
	            case MSR_BPU_CCCR1:		/* disable the PM */
	            case MSR_BPU_CCCR2:		/* disable the PM */
	            case MSR_BPU_CCCR3:		/* disable the PM */
	            case MSR_MS_CCCR0:		/* disable the PM */
	            case MSR_MS_CCCR1:		/* disable the PM */
	            case MSR_MS_CCCR2:		/* disable the PM */
	            case MSR_MS_CCCR3:		/* disable the PM */
	            case MSR_FLAME_CCCR0:	/* disable the PM */
	            case MSR_FLAME_CCCR1:	/* disable the PM */
	            case MSR_FLAME_CCCR2:	/* disable the PM */
	            case MSR_FLAME_CCCR3:	/* disable the PM */
	            case MSR_IQ_CCCR0:		/* disable the PM */
	            case MSR_IQ_CCCR1:		/* disable the PM */
	            case MSR_IQ_CCCR2:		/* disable the PM */
	            case MSR_IQ_CCCR3:		/* disable the PM */
	            case MSR_IQ_CCCR4:		/* disable the PM */
	            case MSR_IQ_CCCR5:		/* disable the PM */
	                pentiumMsrSet (pMsr->addr, (LL_INT *)&zero);
	                break;

	            default:
	                break;
	            }
	        }
	    break;

	default:
	    break;
	}

    return (OK);
    }

/*******************************************************************************
*
* pentiumMcaEnable - enable/disable the MCA (Machine Check Architecture)
*
* This routine enables/disables 1) the Machine Check Architecture and its 
* Error Reporting register banks 2) the Machine Check Exception by toggling
* the MCE bit in the CR4.  This routine works on either P5, P6 or P7 family.
*
* RETURNS: N/A
*/

void pentiumMcaEnable 
    (
    BOOL enable			/* TRUE to enable, FALSE to disable the MCA */
    )
    {
    UINT32 zero[2] = {0x00000000,0x00000000};
    UINT32 one[2]  = {0xffffffff,0xffffffff};
    UINT32 cap[2];		/* MCG_CAP */
    int mcaBanks;		/* MCA Error-Reporting Bank Registers */
    int ix;

    if ((sysCpuId.featuresEdx & CPUID_MCE) == CPUID_MCE)
	{
        if ((sysCpuId.featuresEdx & CPUID_MCA) == CPUID_MCA)
	    {
	    pentiumMsrGet (MSR_MCG_CAP, (LL_INT *)&cap);

	    /* enable/disable all the machine-check features */

	    if (cap[0] & MCG_CTL_P)
		{
		if (enable)
		    pentiumMsrSet (MSR_MCG_CTL, (LL_INT *)&one);
		else
		    pentiumMsrSet (MSR_MCG_CTL, (LL_INT *)&zero);
		}

	    mcaBanks = cap[0] & MCG_COUNT;	/* get number of banks */

	    /* enable all error-logging banks except MC0_CTL register */

	    for (ix = 1; ix < mcaBanks; ix++)
		pentiumMsrSet (MSR_MC0_CTL+(ix * 4), (LL_INT *)&one);
	
	    /* clear all errors */

	    for (ix = 0; ix < mcaBanks; ix++)
		pentiumMsrSet (MSR_MC0_STATUS+(ix * 4), (LL_INT *)&zero);

	    }
	
	/* enable/disable the MCE exception */

	if (enable)
	    vxCr4Set (vxCr4Get () | CR4_MCE);
	else
	    vxCr4Set (vxCr4Get () & ~CR4_MCE);
	}
    }