rcvr.vhd

《51单片机C语言常用模块与综合系统设计实例精讲》的随书光盘。上个星期刚买了这本

--    File Name:  rcvr.vhd
--      Version:  1.1
--         Date:  January 22, 2000
--        Model:  Uart Chip
-- Dependencies:  uart.vhd
--
--      Company:  Xilinx
--
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--                Copyright (c) 2000 Xilinx, Inc.
--                All rights reserved
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity rcvr is
port (rst,clk16x,rxd,rdn : in std_logic ;
	dout : out std_logic_vector (7 downto 0) ;
	data_ready : out std_logic ;
	framing_error : out std_logic ;
	parity_error : out std_logic 
) ;
end rcvr ;

architecture v1 of rcvr is

signal rxd1 : std_logic ;
signal rxd2 : std_logic ;
signal dready_edge : std_logic ;
signal cnt1x :  unsigned (3 downto 0) ;
signal cnt : unsigned (3 downto 0) ;
signal parity : std_logic ;
signal stop_bit : std_logic ;
signal fsm : unsigned (1 downto 0) ;
signal rsr : unsigned (7 downto 0) ;
signal rbr : unsigned (7 downto 0) ;

begin
process (rst,clk16x)
begin
	if rst = '1'then
		rxd1 <= '0' ;
		rxd2 <= '0' ;
		cnt1x<="0000";
		cnt<="0000";		
		parity<='0';  
		dready_edge<='0';
		fsm <="00";
		rsr <= "00000000" ;
		rbr <= "00000000";--"01010101" ;	
	elsif clk16x'event and clk16x = '1' then
		rxd1<=rxd;
		rxd2<=rxd1;
		if(std_logic_vector(fsm)="00")then	--find start bit.
			rsr <= "00000000";
			dready_edge<='0';		
			cnt1x<="0000";
			cnt<="0000";
			if rxd1 = '0' and rxd2 = '1'then
				fsm<="01";				
			end if;
		elsif(std_logic_vector(fsm)="01")then --find start bit center
			cnt<=cnt+"0001";
			if(std_logic_vector(cnt)="1111")then --it is center of start bit.
				fsm<="10";	
			end if;
		elsif(std_logic_vector(fsm)="10")then --  start receive serial data.
			cnt<=cnt+"0001";
			if(std_logic_vector(cnt)="1000")then
				rsr(7) <= rxd2 ; --LSB
				rsr(6 downto 0) <= rsr(7 downto 1) ;
				parity <= parity xor rsr(7) ;	
				cnt1x<=cnt1x+"0001";				
				if(std_logic_vector(cnt1x)="0111")then
					fsm<="11";
			 	end if;
			end if;				
		elsif(std_logic_vector(fsm)="11")then --  start stop bit.
			cnt<=cnt +"0001";
			if(std_logic_vector(cnt)="1000")then
				fsm<="00";				
				rbr <= rsr;
				cnt1x<="0000";
				if rxd2 ='1'then
					dready_edge<='1';
				end if;
			end if;
		else
			fsm<="00";
		end if;
	end if ;
end process  ;


process (rst,rdn,dready_edge)
begin
	if rst = '1'or rdn='0'then
		data_ready<='0';
	elsif dready_edge'event and dready_edge = '1' then
		data_ready<='1';
	end if ;
end process ;

dout <= std_logic_vector(rbr);-- when rdn = '0' else "ZZZZZZZZ" ;
--rxd1<=rxd;

end ;