mypaomadeng.tan.qmsg

该程序实现跑马灯效果,跑马灯共4个状态循环显示

{ "Info" "ITDB_TH_RESULT" "led:inst2\|count\[1\] reset clk -1.494 ns register " "Info: th for register \"led:inst2\|count\[1\]\" (data pin = \"reset\", clock pin = \"clk\") is -1.494 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.565 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.565 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.970 ns) 3.421 ns int_div:inst3\|clk_tem 2 REG LCFF_X1_Y1_N9 2 " "Info: 2: + IC(1.311 ns) + CELL(0.970 ns) = 3.421 ns; Loc. = LCFF_X1_Y1_N9; Fanout = 2; REG Node = 'int_div:inst3\|clk_tem'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.281 ns" { clk int_div:inst3|clk_tem } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.633 ns) + CELL(0.000 ns) 5.054 ns int_div:inst3\|clk_tem~clkctrl 3 COMB CLKCTRL_G3 12 " "Info: 3: + IC(1.633 ns) + CELL(0.000 ns) = 5.054 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'int_div:inst3\|clk_tem~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.633 ns" { int_div:inst3|clk_tem int_div:inst3|clk_tem~clkctrl } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.666 ns) 6.565 ns led:inst2\|count\[1\] 4 REG LCFF_X1_Y13_N9 4 " "Info: 4: + IC(0.845 ns) + CELL(0.666 ns) = 6.565 ns; Loc. = LCFF_X1_Y13_N9; Fanout = 4; REG Node = 'led:inst2\|count\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.511 ns" { int_div:inst3|clk_tem~clkctrl led:inst2|count[1] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 42.28 % ) " "Info: Total cell delay = 2.776 ns ( 42.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.789 ns ( 57.72 % ) " "Info: Total interconnect delay = 3.789 ns ( 57.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.565 ns" { clk int_div:inst3|clk_tem int_div:inst3|clk_tem~clkctrl led:inst2|count[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.565 ns" { clk {} clk~combout {} int_div:inst3|clk_tem {} int_div:inst3|clk_tem~clkctrl {} led:inst2|count[1] {} } { 0.000ns 0.000ns 1.311ns 1.633ns 0.845ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.365 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.365 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 PIN PIN_56 9 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 9; PIN Node = 'reset'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 152 0 168 168 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.316 ns) + CELL(0.370 ns) 7.670 ns led:inst2\|count\[0\]~218 2 COMB LCCOMB_X1_Y13_N10 4 " "Info: 2: + IC(6.316 ns) + CELL(0.370 ns) = 7.670 ns; Loc. = LCCOMB_X1_Y13_N10; Fanout = 4; COMB Node = 'led:inst2\|count\[0\]~218'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.686 ns" { reset led:inst2|count[0]~218 } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.206 ns) 8.257 ns led:inst2\|count\[1\]~219 3 COMB LCCOMB_X1_Y13_N8 1 " "Info: 3: + IC(0.381 ns) + CELL(0.206 ns) = 8.257 ns; Loc. = LCCOMB_X1_Y13_N8; Fanout = 1; COMB Node = 'led:inst2\|count\[1\]~219'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.587 ns" { led:inst2|count[0]~218 led:inst2|count[1]~219 } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.365 ns led:inst2\|count\[1\] 4 REG LCFF_X1_Y13_N9 4 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.365 ns; Loc. = LCFF_X1_Y13_N9; Fanout = 4; REG Node = 'led:inst2\|count\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { led:inst2|count[1]~219 led:inst2|count[1] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 19.94 % ) " "Info: Total cell delay = 1.668 ns ( 19.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.697 ns ( 80.06 % ) " "Info: Total interconnect delay = 6.697 ns ( 80.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.365 ns" { reset led:inst2|count[0]~218 led:inst2|count[1]~219 led:inst2|count[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.365 ns" { reset {} reset~combout {} led:inst2|count[0]~218 {} led:inst2|count[1]~219 {} led:inst2|count[1] {} } { 0.000ns 0.000ns 6.316ns 0.381ns 0.000ns } { 0.000ns 0.984ns 0.370ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.565 ns" { clk int_div:inst3|clk_tem int_div:inst3|clk_tem~clkctrl led:inst2|count[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.565 ns" { clk {} clk~combout {} int_div:inst3|clk_tem {} int_div:inst3|clk_tem~clkctrl {} led:inst2|count[1] {} } { 0.000ns 0.000ns 1.311ns 1.633ns 0.845ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.365 ns" { reset led:inst2|count[0]~218 led:inst2|count[1]~219 led:inst2|count[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.365 ns" { reset {} reset~combout {} led:inst2|count[0]~218 {} led:inst2|count[1]~219 {} led:inst2|count[1] {} } { 0.000ns 0.000ns 6.316ns 0.381ns 0.000ns } { 0.000ns 0.984ns 0.370ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 26 12:45:43 2008 " "Info: Processing ended: Mon May 26 12:45:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}