mypaomadeng.tan.qmsg

该程序实现跑马灯效果,跑马灯共4个状态循环显示

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "int_div:inst3\|clk_tem " "Info: Detected ripple clock \"int_div:inst3\|clk_tem\" as buffer" {  } { { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "int_div:inst3\|clk_tem" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register int_div:inst3\|DCLK_DIV\[6\] register int_div:inst3\|DCLK_DIV\[13\] 175.81 MHz 5.688 ns Internal " "Info: Clock \"clk\" has Internal fmax of 175.81 MHz between source register \"int_div:inst3\|DCLK_DIV\[6\]\" and destination register \"int_div:inst3\|DCLK_DIV\[13\]\" (period= 5.688 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.424 ns + Longest register register " "Info: + Longest register to register delay is 5.424 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst3\|DCLK_DIV\[6\] 1 REG LCFF_X2_Y2_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y2_N17; Fanout = 3; REG Node = 'int_div:inst3\|DCLK_DIV\[6\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_div:inst3|DCLK_DIV[6] } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.483 ns) + CELL(0.651 ns) 1.134 ns int_div:inst3\|LessThan0~656 2 COMB LCCOMB_X2_Y2_N2 1 " "Info: 2: + IC(0.483 ns) + CELL(0.651 ns) = 1.134 ns; Loc. = LCCOMB_X2_Y2_N2; Fanout = 1; COMB Node = 'int_div:inst3\|LessThan0~656'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.134 ns" { int_div:inst3|DCLK_DIV[6] int_div:inst3|LessThan0~656 } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.206 ns) 1.712 ns int_div:inst3\|LessThan0~657 3 COMB LCCOMB_X2_Y2_N0 1 " "Info: 3: + IC(0.372 ns) + CELL(0.206 ns) = 1.712 ns; Loc. = LCCOMB_X2_Y2_N0; Fanout = 1; COMB Node = 'int_div:inst3\|LessThan0~657'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.578 ns" { int_div:inst3|LessThan0~656 int_div:inst3|LessThan0~657 } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.034 ns) + CELL(0.206 ns) 2.952 ns int_div:inst3\|LessThan0~658 4 COMB LCCOMB_X1_Y1_N14 2 " "Info: 4: + IC(1.034 ns) + CELL(0.206 ns) = 2.952 ns; Loc. = LCCOMB_X1_Y1_N14; Fanout = 2; COMB Node = 'int_div:inst3\|LessThan0~658'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.240 ns" { int_div:inst3|LessThan0~657 int_div:inst3|LessThan0~658 } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.577 ns) + CELL(0.206 ns) 3.735 ns int_div:inst3\|LessThan0~661 5 COMB LCCOMB_X2_Y1_N30 29 " "Info: 5: + IC(0.577 ns) + CELL(0.206 ns) = 3.735 ns; Loc. = LCCOMB_X2_Y1_N30; Fanout = 29; COMB Node = 'int_div:inst3\|LessThan0~661'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { int_div:inst3|LessThan0~658 int_div:inst3|LessThan0~661 } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.660 ns) 5.424 ns int_div:inst3\|DCLK_DIV\[13\] 6 REG LCFF_X2_Y2_N31 3 " "Info: 6: + IC(1.029 ns) + CELL(0.660 ns) = 5.424 ns; Loc. = LCFF_X2_Y2_N31; Fanout = 3; REG Node = 'int_div:inst3\|DCLK_DIV\[13\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.689 ns" { int_div:inst3|LessThan0~661 int_div:inst3|DCLK_DIV[13] } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.929 ns ( 35.56 % ) " "Info: Total cell delay = 1.929 ns ( 35.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.495 ns ( 64.44 % ) " "Info: Total interconnect delay = 3.495 ns ( 64.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.424 ns" { int_div:inst3|DCLK_DIV[6] int_div:inst3|LessThan0~656 int_div:inst3|LessThan0~657 int_div:inst3|LessThan0~658 int_div:inst3|LessThan0~661 int_div:inst3|DCLK_DIV[13] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "5.424 ns" { int_div:inst3|DCLK_DIV[6] {} int_div:inst3|LessThan0~656 {} int_div:inst3|LessThan0~657 {} int_div:inst3|LessThan0~658 {} int_div:inst3|LessThan0~661 {} int_div:inst3|DCLK_DIV[13] {} } { 0.000ns 0.483ns 0.372ns 1.034ns 0.577ns 1.029ns } { 0.000ns 0.651ns 0.206ns 0.206ns 0.206ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 2.782 ns int_div:inst3\|DCLK_DIV\[13\] 3 REG LCFF_X2_Y2_N31 3 " "Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X2_Y2_N31; Fanout = 3; REG Node = 'int_div:inst3\|DCLK_DIV\[13\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { clk~clkctrl int_div:inst3|DCLK_DIV[13] } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.92 % ) " "Info: Total cell delay = 1.806 ns ( 64.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.976 ns ( 35.08 % ) " "Info: Total interconnect delay = 0.976 ns ( 35.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl int_div:inst3|DCLK_DIV[13] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst3|DCLK_DIV[13] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 2.782 ns int_div:inst3\|DCLK_DIV\[6\] 3 REG LCFF_X2_Y2_N17 3 " "Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X2_Y2_N17; Fanout = 3; REG Node = 'int_div:inst3\|DCLK_DIV\[6\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { clk~clkctrl int_div:inst3|DCLK_DIV[6] } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.92 % ) " "Info: Total cell delay = 1.806 ns ( 64.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.976 ns ( 35.08 % ) " "Info: Total interconnect delay = 0.976 ns ( 35.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl int_div:inst3|DCLK_DIV[6] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst3|DCLK_DIV[6] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl int_div:inst3|DCLK_DIV[13] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst3|DCLK_DIV[13] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl int_div:inst3|DCLK_DIV[6] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst3|DCLK_DIV[6] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.424 ns" { int_div:inst3|DCLK_DIV[6] int_div:inst3|LessThan0~656 int_div:inst3|LessThan0~657 int_div:inst3|LessThan0~658 int_div:inst3|LessThan0~661 int_div:inst3|DCLK_DIV[13] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "5.424 ns" { int_div:inst3|DCLK_DIV[6] {} int_div:inst3|LessThan0~656 {} int_div:inst3|LessThan0~657 {} int_div:inst3|LessThan0~658 {} int_div:inst3|LessThan0~661 {} int_div:inst3|DCLK_DIV[13] {} } { 0.000ns 0.483ns 0.372ns 1.034ns 0.577ns 1.029ns } { 0.000ns 0.651ns 0.206ns 0.206ns 0.206ns 0.660ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl int_div:inst3|DCLK_DIV[13] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst3|DCLK_DIV[13] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk clk~clkctrl int_div:inst3|DCLK_DIV[6] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst3|DCLK_DIV[6] {} } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "led:inst2\|count\[2\] reset clk 2.262 ns register " "Info: tsu for register \"led:inst2\|count\[2\]\" (data pin = \"reset\", clock pin = \"clk\") is 2.262 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.867 ns + Longest pin register " "Info: + Longest pin to register delay is 8.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 PIN PIN_56 9 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 9; PIN Node = 'reset'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 152 0 168 168 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.316 ns) + CELL(0.370 ns) 7.670 ns led:inst2\|count\[0\]~218 2 COMB LCCOMB_X1_Y13_N10 4 " "Info: 2: + IC(6.316 ns) + CELL(0.370 ns) = 7.670 ns; Loc. = LCCOMB_X1_Y13_N10; Fanout = 4; COMB Node = 'led:inst2\|count\[0\]~218'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.686 ns" { reset led:inst2|count[0]~218 } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.342 ns) + CELL(0.855 ns) 8.867 ns led:inst2\|count\[2\] 3 REG LCFF_X1_Y13_N23 3 " "Info: 3: + IC(0.342 ns) + CELL(0.855 ns) = 8.867 ns; Loc. = LCFF_X1_Y13_N23; Fanout = 3; REG Node = 'led:inst2\|count\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.197 ns" { led:inst2|count[0]~218 led:inst2|count[2] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.209 ns ( 24.91 % ) " "Info: Total cell delay = 2.209 ns ( 24.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.658 ns ( 75.09 % ) " "Info: Total interconnect delay = 6.658 ns ( 75.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.867 ns" { reset led:inst2|count[0]~218 led:inst2|count[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.867 ns" { reset {} reset~combout {} led:inst2|count[0]~218 {} led:inst2|count[2] {} } { 0.000ns 0.000ns 6.316ns 0.342ns } { 0.000ns 0.984ns 0.370ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.565 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.565 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.970 ns) 3.421 ns int_div:inst3\|clk_tem 2 REG LCFF_X1_Y1_N9 2 " "Info: 2: + IC(1.311 ns) + CELL(0.970 ns) = 3.421 ns; Loc. = LCFF_X1_Y1_N9; Fanout = 2; REG Node = 'int_div:inst3\|clk_tem'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.281 ns" { clk int_div:inst3|clk_tem } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.633 ns) + CELL(0.000 ns) 5.054 ns int_div:inst3\|clk_tem~clkctrl 3 COMB CLKCTRL_G3 12 " "Info: 3: + IC(1.633 ns) + CELL(0.000 ns) = 5.054 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'int_div:inst3\|clk_tem~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.633 ns" { int_div:inst3|clk_tem int_div:inst3|clk_tem~clkctrl } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.666 ns) 6.565 ns led:inst2\|count\[2\] 4 REG LCFF_X1_Y13_N23 3 " "Info: 4: + IC(0.845 ns) + CELL(0.666 ns) = 6.565 ns; Loc. = LCFF_X1_Y13_N23; Fanout = 3; REG Node = 'led:inst2\|count\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.511 ns" { int_div:inst3|clk_tem~clkctrl led:inst2|count[2] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 42.28 % ) " "Info: Total cell delay = 2.776 ns ( 42.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.789 ns ( 57.72 % ) " "Info: Total interconnect delay = 3.789 ns ( 57.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.565 ns" { clk int_div:inst3|clk_tem int_div:inst3|clk_tem~clkctrl led:inst2|count[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.565 ns" { clk {} clk~combout {} int_div:inst3|clk_tem {} int_div:inst3|clk_tem~clkctrl {} led:inst2|count[2] {} } { 0.000ns 0.000ns 1.311ns 1.633ns 0.845ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.867 ns" { reset led:inst2|count[0]~218 led:inst2|count[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "8.867 ns" { reset {} reset~combout {} led:inst2|count[0]~218 {} led:inst2|count[2] {} } { 0.000ns 0.000ns 6.316ns 0.342ns } { 0.000ns 0.984ns 0.370ns 0.855ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.565 ns" { clk int_div:inst3|clk_tem int_div:inst3|clk_tem~clkctrl led:inst2|count[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.565 ns" { clk {} clk~combout {} int_div:inst3|clk_tem {} int_div:inst3|clk_tem~clkctrl {} led:inst2|count[2] {} } { 0.000ns 0.000ns 1.311ns 1.633ns 0.845ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led\[0\] led:inst2\|q1\[0\] 11.116 ns register " "Info: tco from clock \"clk\" to destination pin \"led\[0\]\" through register \"led:inst2\|q1\[0\]\" is 11.116 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.565 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.565 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.970 ns) 3.421 ns int_div:inst3\|clk_tem 2 REG LCFF_X1_Y1_N9 2 " "Info: 2: + IC(1.311 ns) + CELL(0.970 ns) = 3.421 ns; Loc. = LCFF_X1_Y1_N9; Fanout = 2; REG Node = 'int_div:inst3\|clk_tem'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.281 ns" { clk int_div:inst3|clk_tem } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.633 ns) + CELL(0.000 ns) 5.054 ns int_div:inst3\|clk_tem~clkctrl 3 COMB CLKCTRL_G3 12 " "Info: 3: + IC(1.633 ns) + CELL(0.000 ns) = 5.054 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'int_div:inst3\|clk_tem~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.633 ns" { int_div:inst3|clk_tem int_div:inst3|clk_tem~clkctrl } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.666 ns) 6.565 ns led:inst2\|q1\[0\] 4 REG LCFF_X1_Y13_N27 5 " "Info: 4: + IC(0.845 ns) + CELL(0.666 ns) = 6.565 ns; Loc. = LCFF_X1_Y13_N27; Fanout = 5; REG Node = 'led:inst2\|q1\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.511 ns" { int_div:inst3|clk_tem~clkctrl led:inst2|q1[0] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 42.28 % ) " "Info: Total cell delay = 2.776 ns ( 42.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.789 ns ( 57.72 % ) " "Info: Total interconnect delay = 3.789 ns ( 57.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.565 ns" { clk int_div:inst3|clk_tem int_div:inst3|clk_tem~clkctrl led:inst2|q1[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.565 ns" { clk {} clk~combout {} int_div:inst3|clk_tem {} int_div:inst3|clk_tem~clkctrl {} led:inst2|q1[0] {} } { 0.000ns 0.000ns 1.311ns 1.633ns 0.845ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.247 ns + Longest register pin " "Info: + Longest register to pin delay is 4.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led:inst2\|q1\[0\] 1 REG LCFF_X1_Y13_N27 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y13_N27; Fanout = 5; REG Node = 'led:inst2\|q1\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { led:inst2|q1[0] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.131 ns) + CELL(3.116 ns) 4.247 ns led\[0\] 2 PIN PIN_6 0 " "Info: 2: + IC(1.131 ns) + CELL(3.116 ns) = 4.247 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'led\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.247 ns" { led:inst2|q1[0] led[0] } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 120 424 600 136 "led\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 73.37 % ) " "Info: Total cell delay = 3.116 ns ( 73.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.131 ns ( 26.63 % ) " "Info: Total interconnect delay = 1.131 ns ( 26.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.247 ns" { led:inst2|q1[0] led[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "4.247 ns" { led:inst2|q1[0] {} led[0] {} } { 0.000ns 1.131ns } { 0.000ns 3.116ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.565 ns" { clk int_div:inst3|clk_tem int_div:inst3|clk_tem~clkctrl led:inst2|q1[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.565 ns" { clk {} clk~combout {} int_div:inst3|clk_tem {} int_div:inst3|clk_tem~clkctrl {} led:inst2|q1[0] {} } { 0.000ns 0.000ns 1.311ns 1.633ns 0.845ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.247 ns" { led:inst2|q1[0] led[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "4.247 ns" { led:inst2|q1[0] {} led[0] {} } { 0.000ns 1.131ns } { 0.000ns 3.116ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}