prev_cmp_mypaomadeng.tan.qmsg

该程序实现跑马灯效果,跑马灯共4个状态循环显示

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "int_div:inst\|clk_tem " "Info: Detected ripple clock \"int_div:inst\|clk_tem\" as buffer" {  } { { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "int_div:inst\|clk_tem" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register int_div:inst\|DCLK_DIV\[12\] register int_div:inst\|DCLK_DIV\[11\] 141.12 MHz 7.086 ns Internal " "Info: Clock \"clk\" has Internal fmax of 141.12 MHz between source register \"int_div:inst\|DCLK_DIV\[12\]\" and destination register \"int_div:inst\|DCLK_DIV\[11\]\" (period= 7.086 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.822 ns + Longest register register " "Info: + Longest register to register delay is 6.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|DCLK_DIV\[12\] 1 REG LCFF_X22_Y7_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y7_N29; Fanout = 3; REG Node = 'int_div:inst\|DCLK_DIV\[12\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_div:inst|DCLK_DIV[12] } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.103 ns) + CELL(0.651 ns) 1.754 ns int_div:inst\|LessThan0~532 2 COMB LCCOMB_X21_Y7_N30 1 " "Info: 2: + IC(1.103 ns) + CELL(0.651 ns) = 1.754 ns; Loc. = LCCOMB_X21_Y7_N30; Fanout = 1; COMB Node = 'int_div:inst\|LessThan0~532'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.754 ns" { int_div:inst|DCLK_DIV[12] int_div:inst|LessThan0~532 } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.366 ns) 2.708 ns int_div:inst\|LessThan0~534 3 COMB LCCOMB_X22_Y7_N0 1 " "Info: 3: + IC(0.588 ns) + CELL(0.366 ns) = 2.708 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 1; COMB Node = 'int_div:inst\|LessThan0~534'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.954 ns" { int_div:inst|LessThan0~532 int_div:inst|LessThan0~534 } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.408 ns) + CELL(0.206 ns) 4.322 ns int_div:inst\|LessThan0~537 4 COMB LCCOMB_X21_Y6_N14 2 " "Info: 4: + IC(1.408 ns) + CELL(0.206 ns) = 4.322 ns; Loc. = LCCOMB_X21_Y6_N14; Fanout = 2; COMB Node = 'int_div:inst\|LessThan0~537'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.614 ns" { int_div:inst|LessThan0~534 int_div:inst|LessThan0~537 } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.577 ns) + CELL(0.206 ns) 5.105 ns int_div:inst\|LessThan0~539 5 COMB LCCOMB_X22_Y6_N30 29 " "Info: 5: + IC(0.577 ns) + CELL(0.206 ns) = 5.105 ns; Loc. = LCCOMB_X22_Y6_N30; Fanout = 29; COMB Node = 'int_div:inst\|LessThan0~539'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { int_div:inst|LessThan0~537 int_div:inst|LessThan0~539 } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.057 ns) + CELL(0.660 ns) 6.822 ns int_div:inst\|DCLK_DIV\[11\] 6 REG LCFF_X22_Y7_N27 3 " "Info: 6: + IC(1.057 ns) + CELL(0.660 ns) = 6.822 ns; Loc. = LCFF_X22_Y7_N27; Fanout = 3; REG Node = 'int_div:inst\|DCLK_DIV\[11\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.717 ns" { int_div:inst|LessThan0~539 int_div:inst|DCLK_DIV[11] } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.089 ns ( 30.62 % ) " "Info: Total cell delay = 2.089 ns ( 30.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.733 ns ( 69.38 % ) " "Info: Total interconnect delay = 4.733 ns ( 69.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.822 ns" { int_div:inst|DCLK_DIV[12] int_div:inst|LessThan0~532 int_div:inst|LessThan0~534 int_div:inst|LessThan0~537 int_div:inst|LessThan0~539 int_div:inst|DCLK_DIV[11] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.822 ns" { int_div:inst|DCLK_DIV[12] {} int_div:inst|LessThan0~532 {} int_div:inst|LessThan0~534 {} int_div:inst|LessThan0~537 {} int_div:inst|LessThan0~539 {} int_div:inst|DCLK_DIV[11] {} } { 0.000ns 1.103ns 0.588ns 1.408ns 0.577ns 1.057ns } { 0.000ns 0.651ns 0.366ns 0.206ns 0.206ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.775 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.775 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.826 ns) + CELL(0.666 ns) 2.775 ns int_div:inst\|DCLK_DIV\[11\] 3 REG LCFF_X22_Y7_N27 3 " "Info: 3: + IC(0.826 ns) + CELL(0.666 ns) = 2.775 ns; Loc. = LCFF_X22_Y7_N27; Fanout = 3; REG Node = 'int_div:inst\|DCLK_DIV\[11\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk~clkctrl int_div:inst|DCLK_DIV[11] } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.08 % ) " "Info: Total cell delay = 1.806 ns ( 65.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.969 ns ( 34.92 % ) " "Info: Total interconnect delay = 0.969 ns ( 34.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.775 ns" { clk clk~clkctrl int_div:inst|DCLK_DIV[11] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.775 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst|DCLK_DIV[11] {} } { 0.000ns 0.000ns 0.143ns 0.826ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.775 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.775 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.826 ns) + CELL(0.666 ns) 2.775 ns int_div:inst\|DCLK_DIV\[12\] 3 REG LCFF_X22_Y7_N29 3 " "Info: 3: + IC(0.826 ns) + CELL(0.666 ns) = 2.775 ns; Loc. = LCFF_X22_Y7_N29; Fanout = 3; REG Node = 'int_div:inst\|DCLK_DIV\[12\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk~clkctrl int_div:inst|DCLK_DIV[12] } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.08 % ) " "Info: Total cell delay = 1.806 ns ( 65.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.969 ns ( 34.92 % ) " "Info: Total interconnect delay = 0.969 ns ( 34.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.775 ns" { clk clk~clkctrl int_div:inst|DCLK_DIV[12] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.775 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst|DCLK_DIV[12] {} } { 0.000ns 0.000ns 0.143ns 0.826ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.775 ns" { clk clk~clkctrl int_div:inst|DCLK_DIV[11] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.775 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst|DCLK_DIV[11] {} } { 0.000ns 0.000ns 0.143ns 0.826ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.775 ns" { clk clk~clkctrl int_div:inst|DCLK_DIV[12] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.775 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst|DCLK_DIV[12] {} } { 0.000ns 0.000ns 0.143ns 0.826ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.822 ns" { int_div:inst|DCLK_DIV[12] int_div:inst|LessThan0~532 int_div:inst|LessThan0~534 int_div:inst|LessThan0~537 int_div:inst|LessThan0~539 int_div:inst|DCLK_DIV[11] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.822 ns" { int_div:inst|DCLK_DIV[12] {} int_div:inst|LessThan0~532 {} int_div:inst|LessThan0~534 {} int_div:inst|LessThan0~537 {} int_div:inst|LessThan0~539 {} int_div:inst|DCLK_DIV[11] {} } { 0.000ns 1.103ns 0.588ns 1.408ns 0.577ns 1.057ns } { 0.000ns 0.651ns 0.366ns 0.206ns 0.206ns 0.660ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.775 ns" { clk clk~clkctrl int_div:inst|DCLK_DIV[11] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.775 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst|DCLK_DIV[11] {} } { 0.000ns 0.000ns 0.143ns 0.826ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.775 ns" { clk clk~clkctrl int_div:inst|DCLK_DIV[12] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.775 ns" { clk {} clk~combout {} clk~clkctrl {} int_div:inst|DCLK_DIV[12] {} } { 0.000ns 0.000ns 0.143ns 0.826ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "led:inst2\|count\[2\] reset clk 2.344 ns register " "Info: tsu for register \"led:inst2\|count\[2\]\" (data pin = \"reset\", clock pin = \"clk\") is 2.344 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.375 ns + Longest pin register " "Info: + Longest pin to register delay is 9.375 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 PIN PIN_56 9 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 9; PIN Node = 'reset'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 152 0 168 168 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.988 ns) + CELL(0.206 ns) 8.178 ns led:inst2\|count\[0\]~218 2 COMB LCCOMB_X20_Y13_N6 4 " "Info: 2: + IC(6.988 ns) + CELL(0.206 ns) = 8.178 ns; Loc. = LCCOMB_X20_Y13_N6; Fanout = 4; COMB Node = 'led:inst2\|count\[0\]~218'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.194 ns" { reset led:inst2|count[0]~218 } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.342 ns) + CELL(0.855 ns) 9.375 ns led:inst2\|count\[2\] 3 REG LCFF_X20_Y13_N19 3 " "Info: 3: + IC(0.342 ns) + CELL(0.855 ns) = 9.375 ns; Loc. = LCFF_X20_Y13_N19; Fanout = 3; REG Node = 'led:inst2\|count\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.197 ns" { led:inst2|count[0]~218 led:inst2|count[2] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.045 ns ( 21.81 % ) " "Info: Total cell delay = 2.045 ns ( 21.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.330 ns ( 78.19 % ) " "Info: Total interconnect delay = 7.330 ns ( 78.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.375 ns" { reset led:inst2|count[0]~218 led:inst2|count[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.375 ns" { reset {} reset~combout {} led:inst2|count[0]~218 {} led:inst2|count[2] {} } { 0.000ns 0.000ns 6.988ns 0.342ns } { 0.000ns 0.984ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.991 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.991 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.466 ns) + CELL(0.970 ns) 3.576 ns int_div:inst\|clk_tem 2 REG LCFF_X21_Y6_N1 2 " "Info: 2: + IC(1.466 ns) + CELL(0.970 ns) = 3.576 ns; Loc. = LCFF_X21_Y6_N1; Fanout = 2; REG Node = 'int_div:inst\|clk_tem'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.436 ns" { clk int_div:inst|clk_tem } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.888 ns) + CELL(0.000 ns) 5.464 ns int_div:inst\|clk_tem~clkctrl 3 COMB CLKCTRL_G5 12 " "Info: 3: + IC(1.888 ns) + CELL(0.000 ns) = 5.464 ns; Loc. = CLKCTRL_G5; Fanout = 12; COMB Node = 'int_div:inst\|clk_tem~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.888 ns" { int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.666 ns) 6.991 ns led:inst2\|count\[2\] 4 REG LCFF_X20_Y13_N19 3 " "Info: 4: + IC(0.861 ns) + CELL(0.666 ns) = 6.991 ns; Loc. = LCFF_X20_Y13_N19; Fanout = 3; REG Node = 'led:inst2\|count\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { int_div:inst|clk_tem~clkctrl led:inst2|count[2] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 39.71 % ) " "Info: Total cell delay = 2.776 ns ( 39.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.215 ns ( 60.29 % ) " "Info: Total interconnect delay = 4.215 ns ( 60.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.991 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl led:inst2|count[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.991 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} led:inst2|count[2] {} } { 0.000ns 0.000ns 1.466ns 1.888ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.375 ns" { reset led:inst2|count[0]~218 led:inst2|count[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "9.375 ns" { reset {} reset~combout {} led:inst2|count[0]~218 {} led:inst2|count[2] {} } { 0.000ns 0.000ns 6.988ns 0.342ns } { 0.000ns 0.984ns 0.206ns 0.855ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.991 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl led:inst2|count[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.991 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} led:inst2|count[2] {} } { 0.000ns 0.000ns 1.466ns 1.888ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led\[1\] led:inst2\|q1\[1\] 13.224 ns register " "Info: tco from clock \"clk\" to destination pin \"led\[1\]\" through register \"led:inst2\|q1\[1\]\" is 13.224 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.991 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.991 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 80 -160 8 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.466 ns) + CELL(0.970 ns) 3.576 ns int_div:inst\|clk_tem 2 REG LCFF_X21_Y6_N1 2 " "Info: 2: + IC(1.466 ns) + CELL(0.970 ns) = 3.576 ns; Loc. = LCFF_X21_Y6_N1; Fanout = 2; REG Node = 'int_div:inst\|clk_tem'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.436 ns" { clk int_div:inst|clk_tem } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.888 ns) + CELL(0.000 ns) 5.464 ns int_div:inst\|clk_tem~clkctrl 3 COMB CLKCTRL_G5 12 " "Info: 3: + IC(1.888 ns) + CELL(0.000 ns) = 5.464 ns; Loc. = CLKCTRL_G5; Fanout = 12; COMB Node = 'int_div:inst\|clk_tem~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.888 ns" { int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.666 ns) 6.991 ns led:inst2\|q1\[1\] 4 REG LCFF_X20_Y13_N1 4 " "Info: 4: + IC(0.861 ns) + CELL(0.666 ns) = 6.991 ns; Loc. = LCFF_X20_Y13_N1; Fanout = 4; REG Node = 'led:inst2\|q1\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { int_div:inst|clk_tem~clkctrl led:inst2|q1[1] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 39.71 % ) " "Info: Total cell delay = 2.776 ns ( 39.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.215 ns ( 60.29 % ) " "Info: Total interconnect delay = 4.215 ns ( 60.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.991 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl led:inst2|q1[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.991 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} led:inst2|q1[1] {} } { 0.000ns 0.000ns 1.466ns 1.888ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.929 ns + Longest register pin " "Info: + Longest register to pin delay is 5.929 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led:inst2\|q1\[1\] 1 REG LCFF_X20_Y13_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y13_N1; Fanout = 4; REG Node = 'led:inst2\|q1\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { led:inst2|q1[1] } "NODE_NAME" } } { "led.vhd" "" { Text "E:/Altera/exercise/mypaomadeng/led.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.803 ns) + CELL(3.126 ns) 5.929 ns led\[1\] 2 PIN PIN_5 0 " "Info: 2: + IC(2.803 ns) + CELL(3.126 ns) = 5.929 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'led\[1\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.929 ns" { led:inst2|q1[1] led[1] } "NODE_NAME" } } { "mypaomadeng.bdf" "" { Schematic "E:/Altera/exercise/mypaomadeng/mypaomadeng.bdf" { { 120 424 600 136 "led\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns ( 52.72 % ) " "Info: Total cell delay = 3.126 ns ( 52.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.803 ns ( 47.28 % ) " "Info: Total interconnect delay = 2.803 ns ( 47.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.929 ns" { led:inst2|q1[1] led[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "5.929 ns" { led:inst2|q1[1] {} led[1] {} } { 0.000ns 2.803ns } { 0.000ns 3.126ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.991 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl led:inst2|q1[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.991 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} led:inst2|q1[1] {} } { 0.000ns 0.000ns 1.466ns 1.888ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.929 ns" { led:inst2|q1[1] led[1] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "5.929 ns" { led:inst2|q1[1] {} led[1] {} } { 0.000ns 2.803ns } { 0.000ns 3.126ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}